DLP470TP datasheet(36/48 Pages) TI1

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VCC

VOFFSET

VRESET

RESET_OEZ

PG_OFFSET

EN_OFFSET

PWRDNZ

and RESETZ

VBIAS

Note 5

Note 8

Note 7

Note 6

Not to scale. Details omitted for clarity

Note 1

Note 4

Delay 1

Note 2

ûV < Specification

Note 3

ûV < Specification

Note 9

Delay 2

VSS

DLP470TP

DLPS105A – JANUARY 2018 – REVISED MAY 2018

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(1)

See Recommended Operating Conditions and the pin functions table.

(2)

To prevent excess current, the supply voltage difference |VOFFSET – VBIAS| must be less than the specified limit in

Recommended Operating Conditions.

(3)

To prevent excess current, the supply difference |VBIAS – VRESET| must be less than the specified limit in the

Recommended Operating Conditions.

(4)

VBIAS should power up after VOFFSET has powered up, per the Delay1 specification in Table 8.

(5)

PG_OFFSET should turn off after EN_OFFSET has turned off, per the Delay2 specification in Table 8.

(6)

DLP controller software enables the DMD power supplies to turn on after RESET_OEZ is at logic high.

(7)

DLP controller software initiates the global VBIAS command.

(8)

After the DMD micromirror park sequence is complete, the DLP controller software initiates a hardware power-down

that activates PWRDNZ and disables VBIAS, VRESET and VOFFSET.

(9)

Under power-loss conditions where emergency DMD micromirror park procedures are being enacted by the DLP

controller hardware, EN_OFFSET may turn off after PG_OFFSET has turned off. The OEZ signal goes high prior to

PG_OFFSET turning off to indicate the DMD micromirror has completed the emergency park procedures.

Figure 14. DMD Power Supply Requirements

DLP470TP Datasheet(PDF) 36 Page - Texas Instruments

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