PC8260 datasheet(23/53 Pages) ATMEL

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PC8260 PowerQUICC II

2131B–HIREL–02/03

IRQ3

DP[3]

CKSTP OUT

EXT BR3

Interrupt Request 3

This input is one of the eight external lines that can request (by means of

the internal interrupt controller) a service routine from the core.

60x Data Parity 3

I/O

The 60x agent that drives the data bus, also drives the data parity

signals. The value driven on the data parity 3 pin should provide odd

parity (odd number of 1’s) on the group of signals that includes data

parity 3 and D[24:31].

Checkstop Output

Assertion of this pin indicates that the core is in its checkstop mode.

External Bus Request 3

An external master should assert this pin to request 60x bus ownership

from the internal arbiter.

IRQ4

DP[4]

CORE SRESET

EXT BG3

Interrupt Request 4

This input is one of the eight external lines that can request (by means of

the internal interrupt controller) a service routine from the core.

60x Data Parity 4

I/O

The 60x agent that drives the data bus, also drives the data parity

signals. The value driven on the data parity 4 pin should provide odd

parity (odd number of 1’s) on the group of signals that includes data

parity 4 and D[32:39].

Core system reset

Asserting this pin will force the core to branch to its reset vector.

External Bus Grant 3

The PowerQUICC II asserts this pin to grant 60x data bus ownership to

an external bus master.

IRQ5

DP[5]

TBEN

EXT DBG3

Interrupt Request 5

This input is one of the eight external lines that can request (by means of

the internal interrupt controller) a service routine from the core.

60x Data Parity 5

I/O

The 60x agent that drives the data bus, also drives the data parity

signals. The value driven on the data parity 5 pin should provide odd

parity (odd number of 1’s) on the group of signals that includes data

parity 5 and D[40:47].

Time Base Enable

This is a count enable input to the Time Base counter in the core.

External Bus Grant3

The PowerQUICC II asserts this pin to grant 60x data bus ownership to

an external bus master.

IRQ6

DP[6]

CSE[0]

Interrupt Request 6

This input is one of the eight external lines that can request (by means of

the internal interrupt controller) a service routine from the core.

60x Data Parity 6

I/O

The 60x agent that drives the data bus, also drives the data parity

signals. The value driven on the data parity 6 pin should provide odd

parity (odd number of 1’s) on the group of signals that include data parity

6 and D[48:55].

Cache Set Entry 0

The cache set entry outputs from the core, represent the cache

replacement set element for the current core transaction reloading into,

or writing out of, the cache.

IRQ7

DP[7]

CSE[1]

Interrupt Request 7

This input is one of the eight external lines that can request (by means of

the internal interrupt controller) a service routine from the core.

60x Data Parity 7

I/O

The 60x master or slave that drives the data bus, also drives the data

parity signals. The value driven on the data parity 7pin should provide

odd parity (odd number of 1’s) on the group of signals that include data

parity 7 and D[56:63].

Cache Set Entry 1

The cache set entry outputs from the core, represent the cache

replacement set element for the current core transaction reloading into,

or writing out of, the cache.

Table 4. External Signals (Continued)

Signal Name

Type

Description

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