PC8260 datasheet(30/53 Pages) ATMEL

30 / 53 page

PC8260 PowerQUICC II

2131B–HIREL–02/03

L_A29

PCI_INTA

Local Bus Address 29

In the local address bus, bit 14 is most significant and bit 31 is least

significant.

PCI INTA

I/O

When the PowerQUICC II is the host in the PCI system, this pin is an

input for delivering PCI interrupts to the host. When the PowerQUICC II

is not the host of the PCI system, this pin is an output used by the

PowerQUICC II to signal an interrupt to the PCI host.

L_A30

Local Bus Address 30

In the local address bus, bit 14 is most significant and bit 31 is least

significant.

L_A31

DLLSYNC

Local Bus Address 31

In the local address bus, bit 14 is most significant and bit 31 is least

significant.

DLL Synchronization

DLLSYNC is used to eliminate skew for the clock driven on CLKOUT.

LCL_D[0:31]

PCI_AD[0:31]

Local Bus Data

I/O

In the local data bus, bit 0 is most significant and bit 31 is least

significant.

PCI Address Data

I/O

PCI bus address data input/output pins. In the PCI address data bus, bit

31 is most significant and bit 0 is least significant.

LCL_DP[0:3]

PCI_C/BE[0:3]

Local Bus Data Parity

I/O

In local bus write operations the PowerQUICC II drives these pins. In

local bus read operations the accessed device drives these pins.

LCL_DP(0) is driven with a value that gives odd parity with LCL_D(0:7).

LCL-DP(1) is driven with a value that gives odd parity with LCL_D(8:15).

LCL_DP(2) is driven with a value that gives odd parity with

LCL_D(16:23).

LCL_DP(3) is driven with a value that gives odd parity with

LCL_D(24:31)

PCP Command/Byte

Enable

I/O

The PowerQUICC II drives these pins when it is the initiator of a PCI

transfer.

IRQ0

NMI_OUT

Interrupt request 0

This input is one of the eight external lines that can request (by means of

the NMI-OUT internal interrupt controller) a service routine from the

core.

Non Maskable Interrupt

Output

This is an output driven from PowerQUICC II’s internal interrupt

controller. Assertion of this output indicates that an unmasked interrupt

is pending in PowerQUICC II’s internal interrupt controller.

IRQ7

INT_OUT

APE

Interrupt Request 7

This input is one of the eight external lines that can request (by means of

the internal interrupt controller) a service routine from the core.

Interrupt Output

This is an output driven from PowerQUICC II’s internal interrupt

controller. Assertion of this output indicates that an unmasked interrupt

is pending in PowerQUICC II’s internal interrupt controller.

Address Parity Error

This output pin will be asserted when the PowerQUICC II’s detects

wrong parity driven on its address parity pins by an external master

TRST

Test Reset (JTAG)

This is the reset input to PowerQUICC II’s JTAG/COP controller.

TCK

Test Clock (JTAG)

This pin provides the clock input for PowerQUICC II’s JTAG/COP

controller.

TMS

Test Mode Select (JTAG)

This pin controls the state of PowerQUICC II’s JTAG/COP controller.

TDI

Test Data In (JTAG)

This pin is the data input to PowerQUICC II’s JTAG/COP controller.

TDO

Test Data Out (JTAG)

This pin is the data output from PowerQUICC II’s JTAG/COP controller.

Table 4. External Signals (Continued)

Signal Name

Type

Description

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