PC8260 datasheet(28/53 Pages) ATMEL

28 / 53 page

PC8260 PowerQUICC II

2131B–HIREL–02/03

L_A14

PCI_PAR

Local Bus Address 14

In the local address bus, bit 14 is most significant and bit 31 is least

significant.

PCI Parity

I/O

Assertion of this pin indicates that odd parity is driven across

PCI_AD[0:31] and PCI_C/BE[0-3] during address and data phases.

Negation of this pin indicates that even parity is driven across the

PCI_AD[0-31] and PCI_C/BE[0-3] signals during address and data

phases.

L_A15

PCI_FRAME

SMI

Local Bus Address 15

In the local address bus, bit 14 is most significant and bit 31 is least

significant.

PCI Frame i

I/O

This pin is driven by the PowerQUICC II when its interface is the initiator

of a PCI transfer. This pin is asserted to indicate that a PCI transfer is on

going.

System Management

Interrupt

System management interrupt input to the core.

L-A16

PCI_TRDY

Local Bus Address 16

In the local address bus, bit 14 is most significant and bit 31 is least

significant.

PCI Target Ready

I/O

This pin is driven by the PowerQUICC II when its PCI interface is the

target of a PCI transfer. Assertion of this pin indicates that the PCI target

is ready to send or accept a data beat.

L_A17

PCI_IRDY

CKSTP_OUT

Local Bus Address 17

In the local address bus, bit 14 is most significant and bit 31 is least

significant.

PCI Initiator Ready

I/O

This pin is driven by the PowerQUICC II when its PCI interface is the

initiator of a PC] transfer. Assertion of this pin indicates that the PCI

initiator is ready to send or accept a data beat.

Checkstop Output

Assertion of CKSTP_OUT indicates the core is in checkstop mode.

L_A18

PCI_STOP

Local Bus Address 18

In the local address bus, bit 14 is most significant and bit 31 is least

significant.

PCI Stop

I/O

This pin is driven by the PowerQUICC II when its PCI interface is the

target of a PCI transfer. Assertion of this pin indicates that the PCI target

is requesting to stop the PCI transfer.

L_A19

PCI_DEVESEL

Local Bus Address 19

In the local address bus, bit 14 is most significant and bit 31 is least

significant.

PCI Device Select

I/O

This pin is driven by the PowerQUICC II when its PCI interface is the

target of a PCI transfer. Assertion of this pin indicates that a PCI target

has recognized a new PCI transfer with an address that belongs to the

PCI target.

L_A20

PCI_IDSEL

Local Bus Address 20

In the local address bus, bit 14 is most significant and bit 31 is least

significant.

PCI ID select

Used to select PowerQUICC II’s PCI interface during a PCI configuration

cycle.

L_A21

PCI_PERR

Local Bus Address 21

In the local address bus, bit 14 is most significant and bit 31 is least

significant.

PCI Parity Error

I/O

Assertion of this pin indicates that a parity error was detected during a

PCI transfer.

Table 4. External Signals (Continued)

Signal Name

Type

Description

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