SCD1284 datasheet(108/176 Pages) INTEL

108 / 176 page

CD1284 — IEEE 1284-Compatible Parallel Interface Controller

108

Datasheet

7.0

Detailed Register Descriptions

This section presents a complete and detailed description of each register. Registers have two

formats: 1) full eight bits, where the entire content defines a single function; 2) the register is a

collection of bits, grouped singly or in multiples, defining a function. In the second format, the

descriptions divide the register into its component parts and describe the bits individually. The

order of register presentation corresponds to the register summary tables in Chapter 4.0.

7.1

Global Registers

7.1.1

Channel Access Register

The CAR provides access to individual channels within the CD1284. The least-significant two bits

of the register select one of the four channels. Before any operation that affects a channel, this

Bits 7:3 are not used except during Poll-mode operation (see Section 6.3 for details).

7.1.2

Global Firmware Revision Code Register

The GFRCR serves two purposes in the CD1284. First, it displays the revision number of the

firmware in the chip. When a revision to the CD1284 is required, the revision number of the

firmware is incremented by one. The revision code is 24 (hex) for the Revision D device, and 25

(hex) for the Revision E device.

Access: Read/Write

8-Bit Hex Address: 68

Default Value: XX

Bit 7Bit 6Bit 5Bit 4Bit 3

Bit 2Bit 1

Bit 0

Poll

Channel Selected

Channel 0

Not used

Channel 2

Channel 3

Access: Read/Write

8-Bit Hex Address: 4F

Default Value: 25

Bit 7Bit 6Bit 5

Bit 4

Bit 3Bit 2Bit 1Bit 0

Firmware Revision Code

SCD1284 Datasheet(PDF) 108 Page - Intel Corporation

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