SCD1284 datasheet(109/176 Pages) INTEL

109 / 176 page

IEEE 1284-Compatible Parallel Interface Controller — CD1284

Datasheet

109

Secondly, a system programmer can use this register to indicate when the internal processor

completes reset procedures. This is done by a power-on reset (by the RESET* input) or a software

global reset (by the reset command in the CCR). Immediately after the reset operation begins, the

internal CPU clears the register. When complete, and the CD1284 is ready to accept host accesses,

the register is loaded with the revision code.

7.1.3

General-Purpose I/O Direction Register

7.1.4

General-Purpose I/O Register

This pair of registers enables access and control of the general-purpose I/O port. The general-

purpose I/O port provides a byte-wide general purpose set of signals that are individually direction

programmable.

The GPIO register accesses the data port on pins 53–60 (G[7:0]) with Data 0 accessing GP[0], etc.

The corresponding bit in the GPDIR register controls the direction of the associated signal; ‘1’

programs the signal as output and ‘0’ programs it as input. When writing to the GPIO register, ‘1’s

and ‘0’s are reflected in their true states on the pins that are programmed as outputs. When reading

from the GPIO register, bits programmed as inputs reflect the true state of the signal condition on

those bits; bits programmed as output reflect the previously set state.

7.1.5

Modem Interrupting Channel Register

The MICR, RISR, and TICR indicate the serial channel number that is currently being serviced by

an active acknowledge cycle (whether polled or interrupt). Bits 3:2 (C1 and C0) are only valid

during the context of a channel service routine; at any other time, their state is undefined. Host

system software uses these registers to determine the number of the channel that originated the

particular service request (receive, transmit, or modem). The format of these registers is the same

and the description is valid for each. The upper four bits and lower two bits are user-defined and

can be set to any value desired. When the register is read, these bits are presented as defined by the

user; C1 and C0 are set by the CD1284 to reflect the proper channel number.

Access: Read/Write

8-Bit Hex Address: 71

Default Value: 00

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Dir 7

Dir 6

Dir 5

Dir 4

Dir 3

Dir 2

Dir 1

Dir 0

Access: Read/Write

8-Bit Hex Address: 70

Default Value: 00

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

Access: Read/Write

8-Bit Hex Address: 46

Default Value: 00

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

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SCD1284 Datasheet(PDF) 109 Page - Intel Corporation

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