SCD1284 datasheet(111/176 Pages) INTEL

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IEEE 1284-Compatible Parallel Interface Controller — CD1284

Datasheet

111

7.1.7

Parallel Interrupt Register

The PIR is a modified version of the other interrupt registers (RIR, TIR, and MIR) that

incorporates the unique differences between interrupt structures of the two major blocks of the

CD1284. The Ireq bit (bit 7) has the identical function as the Ireq bits in the TIR, RIR, and MIR.

7.1.8

Prescaler Period Register

The PPR sets the divisor that generates the time period for CD1284 timer operations. It can be set

to any value between 0 and 255 (x’FF). The PPR is clocked by the system clock prescaled

(divided) by 512.

Rxunfair, Txunfair, and Mdunfair: These bits are used by the internal processor to implement the Fair Share

service request function. If this bit is set, the CD1284 does not assert another service request of this type until

the bit is cleared by a pulse on the external SVCACK* pin. The unfair bits are forced to ‘0’, disabling the Fair

Share mechanism, by setting the Unfair bit in the PACR. These bits are not used in Poll mode.

4:2

These bits define the context of the current service-acknowledge cycle during Poll mode and are fixed by

hardware within the CD1284. These bits must be replicated exactly when the register is copied to the CAR

and is activating a service-acknowledge cycle. See the discussion of Poll-mode operation in Section 5.3 for a

more detailed description.

1:0

ch[1:0]: These two bits encode the channel number of the requesting channel. During Poll-mode operation

when the RIR, TIR, and MIR are copied into the CAR to start the service routine, ch[1:0] set the channel

number that is serviced.

Access: Read/Write

8-Bit Hex Address: 61

Default Value: 00

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

PPIreq

PPort

Pipeline

00000

Bit

Description

Bit

Description

PPIreq: The internal processor sets this bit to generate the external service request output. It is a direct

reflection of the inverse state of the SVCREQP* pin; it is the active-high output of the latch that drives

SVCREQP*. This bit can be scanned by the host to detect an active service request. The bit is cleared by the

internal logic at the beginning of the hardware service-acknowledge cycle or by toggling the IntEn bit

(PFCR[4]).

6:5

PPort and Pipeline: These two bits indicate which of the two functional blocks of the parallel port are

requesting service. PPort set indicates that the parallel channel control state machine is the cause of the

request; Pipeline set indicates that the data pipeline is requesting service. Both bits set indicates that both

blocks are requesting service simultaneously.

4:0

Reserved: These bits always return ‘0’ when read by the host. Do not modify.

Access: Read/Write

8-Bit Hex Address: 7E

Default Value: FF

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

8-bit Binary Value

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