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SCD1284 Datasheet(PDF) 114 Page - Intel Corporation |
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SCD1284 Datasheet(HTML) 114 Page - Intel Corporation |
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114 / 176 page ![]() CD1284 — IEEE 1284-Compatible Parallel Interface Controller 114 Datasheet Virtual Registers — Serial 7.2.1 Modem Interrupt Status Register The MISR provides the status regarding a modem service request. If the modem-signal change detections (zero-to-one or one-to-zero transition) are enabled in MCOR1 or MCOR2, the change causes a service request and the changed signal is flagged in this register. 7.2.2 Modem Interrupt Vector Register The value in this register is placed on the data bus, DB[7:0], when SVCACKM* is activated in response to an active SVCREQM*. See Section 7.4.6 on page 128 for more details on the LIVR. Register Name: MISR Register Description: Modem Interrupt Status Access: Read only 8-Bit Hex Address: 4C Default Value: 00 Bit 7Bit 6 Bit 5 Bit 4Bit 3Bit 2Bit 1Bit 0 DSRch CTSch RIch CDch 0000 Bit Description 7 Data Set Ready Change: An enabled transition on the Data Set Ready signal causes this bit to be set and a modem service request posted. 6 Clear To Send Change: An enabled transition on the Clear To Send signal causes this bit to be set and a modem service request posted. 5 Ring Indicator Change: An enabled transition on the Ring Indicator signal causes this bit to be set and a modem service request posted. 4 Carrier Detect Change: An enabled transition on the Carrier Detect signal causes this bit to be set and a modem service request posted. 3:0 These read-only bits always return ‘0’. Register Name: MIVR Register Description: Modem Interrupt Vector Access: Read only 8-Bit Hex Address: 41 Default Value: 00 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X XXX X IT2 IT1 IT0 IT2 IT1 IT0 Description 0 0 0 No modem interrupts. 0 0 1 Group 1: Modem signal change service request. 01 0 Invalid. ll l 11 1 |
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