SCD1284 datasheet(116/176 Pages) INTEL

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CD1284 — IEEE 1284-Compatible Parallel Interface Controller

116

Datasheet

provides the character. It is not necessary to read either of these values. If the service acknowledge

is terminated without reading the exception status and data from the RDSR, the internal processor

updates the FIFO pointers as if the status/data were read. The same is true when only the status is

read. Overrun errors are an exception to this (see table below).

7.2.5

Receive Interrupt Vector Register

The value in this register is placed on the data bus, DB[7:0], when SVCACKR* is activated in

response to an active SVCREQR*. See Section 7.4.6 on page 128 for more details on the LIVR.

Bit

Description

Timeout: If the service request enable for timeout is set, this bit indicates that no data has been received

within the receive timeout period set by the RTPR after the last character was removed.

6:4

Special Character Detect: These three bits are encoded as follows:

NOTE: No special character matching is performed if either a parity (PE) or framing (FE) error occur unless

CMOE is enabled by COR5[5].

Break: Indicates that a break was detected.

Parity Error: Indicates that a character was received with parity other than that programmed in COR1.

Framing Error: Indicates that the character was received with a bad stop bit.

Overrun Error: This bit is set if new data is received, but there is no space available in the FIFO and Holding

before the overrun occurred. Thus, the character read on the subsequent read from the RDSR is good data

and should not be discarded.

Access: Read only

8-Bit Hex Address: 43

Default Value: 00

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

XXX

IT2

IT1

IT0

SCDet2

SCDet1

SCDet0

Status

None detected.

Special character 1 matched.

Special character 2 matched.

Special character 3 matched.

Special character 4 matched.

Not used.

End-of-break detected.

Range detect.

IT2

IT1

IT0

Description

No receive interrupt active.

Invalid.

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