SCD1284 datasheet(119/176 Pages) INTEL

119 / 176 page

IEEE 1284-Compatible Parallel Interface Controller — CD1284

Datasheet

119

7.3.1.1

Format 1 — Reset Channel Command

When bit 7 is set, one of three types of reset operations are initiated, based on the value of the least-

significant two bits. Bit 0 sets the type of reset, either channel-only or full-chip, and bit 1 causes the

FIFO of the selected channel to be flushed.

The two types of reset selected by bit 0 cause very different results. When bit 0 is ‘0’, the reset

command effects only the selected channel. Resetting a channel disables both the receiver and

transmitter, and all FIFOs are flushed (cleared). If bit 0 is ‘1’, a full-chip reset is initiated. This reset

has the same results as a hardware reset caused by activation of RESET*: all channels are disabled,

all FIFOs are flushed, and all control registers set to their power-on reset state.

The completion of the reset operation can be detected the same way as though a power-on or

hardware reset had occurred: the GFRCR changes from zero to the value of the firmware revision.

Note that at the start of the reset operation, the GFRCR is cleared, but it can take some time for this

to occur. Host software should wait for the GFRCR to go to zero, and then wait for it to go non-

zero to indicate that the reset operation is complete. The host can clear the GFRCR before issuing

the reset command and then wait for it to become non-zero.

The FTF (flush serial transmit FIFO) command, bit 1, causes the serial transmit FIFO of the

selected channel to be cleared and pointers reset to the empty state. Any data in the FIFO is lost.

7.3.1.2

Format 2 — Channel Option Register Change Command

Bit 6 – combined with any bits 3:1 – informs the MPU that a change occurred in one of the Channel

Option registers, COR1, COR2, and/or COR3, respectively. It is permissible to indicate that more

than one COR has changed.

This command exists so that changes in the CORs are noted by the MPU, allowing it to update its

internal working register, since it keeps copies of the CORs in its own shadow registers.

Bit 7

Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

Res Chan

000

FTF

Type

Bit

Description

This bit must always be ‘1’.

6:2

These bits must always be ‘0’.

1:0

These bits are encoded as:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

COR Chg

COR3

COR2

COR1

FTF

Type

Function

Reset current channel.

Full CD1284 reset.

Flush serial transmit FIFO of current channel

Not used.

SCD1284 Datasheet(PDF) 119 Page - Intel Corporation

SCD1284 Datasheet(HTML) 119 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL