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SCD1284 Datasheet(PDF) 122 Page - Intel Corporation |
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SCD1284 Datasheet(HTML) 122 Page - Intel Corporation |
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122 / 176 page ![]() CD1284 — IEEE 1284-Compatible Parallel Interface Controller 122 Datasheet 7.3.2 Channel Control Status Register The CCSR provides current receiver/transmitter status of the selected channel. Bit Description 7:5 Must be ‘0’. 4 Must be ‘1’. 3:0 Select channel enable/disable activity: Register Name: CCSR Register Description: Channel Control Status Access: Read only 8-Bit Hex Address: 0B Default Value: 00 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RxEN RxFloff RxFlon 0 TxEN TxFloff TxFlon 0 XMT EN XMT DIS RCV EN RCV DIS Encoding 0 0 0 1 Disable receiver. 0 0 1 0 Enable receiver. 0 1 0 0 Disable transmitter. 1 0 0 0 Enable transmitter. 0 1 0 0 Disable transmitter and receiver. 0 1 1 0 Disable transmitter; enable receiver. 1 0 0 1 Enable transmitter; disable receiver. 1 0 1 0 Enable transmitter and receiver. Bit Description 7 Receiver Enabled: This bit is set when the receiver is enabled and cleared when it is disabled. 6 Receiver Flow Off: This bit indicates that the receiver has requested the remote to stop transmitting through the use of a send XOFF character by a send special character 2 command in the CCR. The bit is cleared when a send special character 1 (XON) command is issued; the channel is either enabled or disabled, or the channel is reset. 5 Receiver Flow On: When a send special character 1 (XON) command is issued by the CCR, this bit is set. This bit is cleared when one of three events has occurred, 1) the first non-flow control character is received, 2) the receiver is either enabled or disabled, 3) or the channel is reset. 4 Reserved: This bit returns ‘0’ when read. 3 Transmitter Enabled: This bit is set when the transmitter is enabled and cleared when it is disabled. |
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