SCD1284 datasheet(125/176 Pages) INTEL

125 / 176 page

IEEE 1284-Compatible Parallel Interface Controller — CD1284

Datasheet

125

7.4.3

Channel Option Register 3

Note:

The threshold for the parallel channel (channel 0) are set by the PFTR.

Local Loopback Mode: This bit enables local loopback of the channel. This mode is generally used during

system diagnostics. If this bit is set, the transmitter is internally ‘looped’ back to the receiver. The TxD pin is

set to the marking state. Data sent is immediately received by the receiver. No data appears on the TxD pin;

data on the RxD pin is ignored.

Remote Loopback Mode: Remote loopback allows a remote system to test its serial data stream. If this

function is enabled, the CD1284 internally connects its receiver to the transmitter. Any data received is

immediately echoed back. This mode is enabled by setting RLM, and disabled by clearing RLM.

Request To Send Automatic Output: The CD1284 can automatically assert RTS when a channel is

enabled (by transmit/receive enable command in the CCR) and there is data in the FIFO. When the channel

is disabled or there is no more data to send (that is, in the FIFO or Holding and Shift registers), RTS* is

negated. Setting RtsAO enables the function.

Clear To Send Automatic Enable: This bit enables the CTS* input to control transmitter operation. If CtsAE

is set and CTS* is not asserted, character transmission does not proceed.

Data Set Ready Automatic Enable: This bit allows the DSR* input to control receiver operation. Setting

DsrAE enables the function. When enabled and DSR* is deasserted, the CD1284 discards all received

characters.

Access: Read/Write

8-Bit Hex Address: 0A

Default Value: 00

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SCDRNG

SCD34

FCT

SCD12

RxTh3

RxTh2

RxTh1

RxTh0

Bit

Description

Special Character Detect Range: This bit enables range checking on received characters. If the character

falls between a lower range, set by the value stored in the SCRL register, and an upper range, set by the

value stored in the SCRH register – inclusive, a receive exception service request is posted with the status

indicating a range detect (RDSR bits SCDet2–SCDet0

= 111).

Enable Special Character Detect on SCHR4 and SCHR3: This bit controls whether or not the CD1284

performs a comparison on received characters against the values stored in SCHR4 and SCHR3. The

comparison is enabled by this bit being ‘1’.

Bit

Description

SCD1284 Datasheet(PDF) 125 Page - Intel Corporation

SCD1284 Datasheet(HTML) 125 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL