SCD1284 datasheet(123/176 Pages) INTEL

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IEEE 1284-Compatible Parallel Interface Controller — CD1284

Datasheet

123

7.4

Channel Registers — Parallel Pipeline

The following five Channel Option registers control many aspects of CD1284 serial channel

operation and enable special character processing features. COR4 and COR5 specifically enable

the UNIX line discipline character handling functions.

7.4.1

Channel Option Register 1

Transmitter Flow Off: This bit indicates that the CD1284 has been requested to stop transmission by the

remote (received in-band flow control character XOFF). The bit is cleared when the CD1284 requests to

restart transmission (receives an XON character); the channel is either enabled or disabled, or the channel is

reset.

Transmitter Flow On: This bit is set when the CD1284 requests to restart transmission (received an XON

character). It is reset when transmission begins, when the channel is either enabled or disabled, or when the

channel is reset.

Reserved: This bit returns ‘0’ when read.

Bit

Description

Access: Read/Write

8-Bit Hex Address: 08

Default Value: 00

Bit 7

Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

Parity

ParM1

ParM0

Ignore

Stop1

Stop0

ChL1

ChL0

Bit

Description

Parity Type: This bit selects the type of parity that is generated and checked if parity is enabled. ‘1’ selects

odd parity and ‘0’ selects even parity.

6:5

Parity Mode 1 and Parity Mode 0: These bits define the parity operation for both the transmitter and

receiver. The encoding is:

ParM1

ParM0

Function

No parity.

Force parity (odd parity = force 1, even parity = force 0).

Normal parity.

Not used.

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