SCD1284 datasheet(118/176 Pages) INTEL

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CD1284 — IEEE 1284-Compatible Parallel Interface Controller

118

Datasheet

Virtual Registers — All

7.2.8

End of Service Request Register

The EOSRR is a dummy location used to signal the end of a hardware service-acknowledge

procedure invoked by the activation of SVCACK*. The data pattern written is a ‘don’t care’ value.

A write to this location causes the CD1284 to perform its internal switch out of the service-

acknowledge context. This register is only used during a hardware-activated service acknowledge

and must not be written during Poll-mode operation.

7.3

Channel Registers

Each of the four channels has a set of registers that control aspects of its operation. In the following

being accessed at any given time is controlled by the CAR. This is true even during a service-

acknowledge context; the CAR points to the channel to be serviced, whether it was loaded by the

host (during Poll-mode operation) or by the CD1284 itself (during a hardware-activated service

acknowledge).

7.3.1

Channel Command Register

The CCR issues commands directly to the on-chip processor to control or change some channel

and, in one case, global functions of the channel selected by the CAR. The upper four bits indicate

which of four command types is being issued and the lower four bits are parameters to those

commands. No more than one bit is ever set in the command type field. When the command is

executed by the CD1284, it zeros out the CCR. Therefore, two consecutive commands must wait

for the CCR to clear after the first is issued, before the second command is issued.

Note:

The CCR is valid only for serial channels 2 and 3. Commands issued to the CCR location of the

parallel channel (channel 0) or channel 1 are ignored by the MPU and have no effect on device

operation. If the host needs to issue a full device reset, it must select either channel 2 or channel 3

before issuing the command.

Access: Write only

8-Bit Hex Address: 60

Default Value: XX

Bit 7Bit 6Bit 5Bit 4Bit 3

Bit 2Bit 1

Bit 0

Access: Read/Write

8-Bit Hex Address: 05

Default Value: 00

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Res Chan

COR Chg

Send SC

Chan Ctl

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