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SCD1284 Datasheet(PDF) 117 Page - Intel Corporation

Part # SCD1284
Description  IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
PDF  176 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

SCD1284 Datasheet(HTML) 117 Page - Intel Corporation

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IEEE 1284-Compatible Parallel Interface Controller — CD1284
Datasheet
117
7.2.6
Transmit Data Register
The transmit data register is the port for the host to write to the transmit FIFO. When a channel is
being serviced for a transmit service request, the host can write up to 12 characters to this register.
The transmit data register should only be written during the context of a transmit-service
acknowledge. A write of data to this location at any other time yields unpredictable results.
7.2.7
Transmit Interrupt Vector Register
The value in this register is placed on the data bus, DB[7:0], when SVCACKT* is activated in
response to an active SVCREQT*. See Section 7.4.6 on page 128 for more details on the LIVR.
0
1
1
Group 3: Received good data service request.
100
Invalid.
lll
110
1
1
1
Group 3: Received exception data service request.
Register Name: TDR
Register Description: Transmit Data
Access: Write only
8-Bit Hex Address: 63
Default Value: 00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Transmit Character
IT2
IT1
IT0
Description
Register Name: TIVR
Register Description: Transmit Interrupt Vector
Access: Read only
8-Bit Hex Address: 42
Default Value: 00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
XXX
XX
IT2
IT1
IT0
IT2
IT1
IT0
Description
0
0
0
No transmit interrupt active.
0
0
1
Invalid.
0
1
0
Group 2: Transmit data service request.
11
1
Invalid.
lll
11
1



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