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SCD1284 Datasheet(PDF) 112 Page - Intel Corporation |
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SCD1284 Datasheet(HTML) 112 Page - Intel Corporation |
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112 / 176 page  CD1284 — IEEE 1284-Compatible Parallel Interface Controller 112 Datasheet Note: This value does not have any effect on baud rate generation. The time period generated by this register drives the receive timer and activates the ‘no new data’ and ‘receive data timeout’ interrupts. See the receiver operation discussion in Chapter 5.0 for a description of receiver timer functions. 7.1.9 Receive Interrupting Channel Register See Section 7.1.5 on page 109, the description of the MICR, for details on the RICR. 7.1.10 Receive Interrupt Register See Section 7.1.6 on page 110, the description of the MIR, for details on the RIR. 7.1.11 Service Request Register The SVRR reflects the inverse of the state of the service request pins (SVCREQR*, SVCREQT*, and SVCREQM*). Its primary use is in polled systems, and it allows system software to determine what, if any, service requests are pending. Register Name: RICR Register Description: Receive Interrupting Channel Access: Read/Write 8-Bit Hex Address: 44 Default Value: 00 765 4321 0 X XXX C1 C0 XX Register Name: RIR Register Description: Receive Interrupt Access: Read/Write 8-Bit Hex Address: 6B Default Value: 18 Bit 7Bit 6Bit 5 Bit 4 Bit 3Bit 2Bit 1Bit 0 RxIreq Rxbusy Rxunfair 1 1 0 ch[1] ch[0] Register Name: SVRR Register Description: Service Request Access: Read only 8-Bit Hex Address: 67 Default Value: 00 Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 DMAREQ ExtM ExtT ExtR SRP SRM SRT SRR Bit Description 7 DMA Request Status: ‘1’ indicates request pending. 6 ExtM: Reflects the current state of the external SVCREQM* signal. 5 ExtT: Reflects the current state of the external SVCREQT* signal. 4 ExtR: Reflects the current state of the external SVCREQR* signal. 3 Service Request Parallel: ‘1’ indicates request pending. |
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