RFPIC12C509AF datasheet(29/104 Pages) MICROCHIP

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Preliminary

DS70031A-page 27

rfPIC12C509AG/509AF

6.0

TIMER0 MODULE AND TMR0

The Timer0 module has the following features:

• 8-bit timer/counter register, TMR0

- Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

- Edge select for external clock

Figure 6-1 is a simplified block diagram of the Timer0

module.

Timer mode is selected by clearing the T0CS bit

(OPTION<5>). In timer mode, the Timer0 module will

increment every instruction cycle (without prescaler). If

TMR0 register is written, the increment is inhibited for

the following two instruction cycles (Figure 6-2 and

Figure 6-3). The user can work around this by writing

an adjusted value to the TMR0 register.

Counter mode is selected by setting the T0CS bit

(OPTION<5>). In this mode, Timer0 will increment

either on every rising or falling edge of pin T0CKI. The

T0SE bit (OPTION<4>) determines the source edge.

Clearing the T0SE bit selects the rising edge. Restric-

tions on the external clock input are discussed in detail

in Section 6.1.

The prescaler may be used by either the Timer0 mod-

ule or the Watchdog Timer, but not both. The prescaler

assignment is controlled in software by the control bit

PSA (OPTION<3>). Clearing the PSA bit will assign the

prescaler to Timer0. The prescaler is not readable or

writable. When the prescaler is assigned to the Timer0.

FIGURE 6-1:

TIMER0 BLOCK DIAGRAM

Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.

2: The prescaler is shared with the Watchdog Timer (Figure 6-5).

T0CS(1)

FOSC/4

Programmable

Prescaler(2)

Sync with

Internal

Clocks

TMR0 reg

PSout

(2 TCY delay)

PSout

Data bus

PSA

(1)

PS2, PS1, PS0(1)

Sync

T0SE

GP2/T0CKI

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