RFPIC12C509AF datasheet(17/104 Pages) MICROCHIP

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Preliminary

DS70031A-page 15

rfPIC12C509AG/509AF

4.0

MEMORY ORGANIZATION

rfPIC12C509AG/509AF memory is organized into pro-

gram memory and data memory. For devices with more

than 512 bytes of program memory, a paging scheme

is used. Program memory pages are accessed using

one STATUS register bit. For the rfPIC12C509AG/

509AF, with a data memory register file of more than 32

registers, a banking scheme is used. Data memory

banks are accessed using the File Select Register

(FSR).

4.1

Program Memory Organization

The rfPIC12C509AG/509AF devices have a 12-bit Pro-

gram Counter (PC) capable of addressing a 2K x 12

program memory space.

Only the first 1K x 12 (0000h-03FFh) for the

rfPIC12C509AG/509AF is physically implemented.

Refer to Figure 4-1. Accessing a location above these

boundaries will cause a wrap-around within the first 1K

x 12 space. The effective RESET vector is at 000h,

(see Figure 4-1). Location 03FFh contains the internal

clock oscillator calibration value. This value should

never be overwritten.

FIGURE 4-1: PROGRAM MEMORY MAP AND

STACK

CALL, RETLW

PC<11:0>

Stack Level 1

Stack Level 2

0000h

7FFh

01FFh

0200h

On-chip Program

Memory

RESET Vector (note 1)

Note 1: Address 0000h becomes the

effective RESET vector. Location

03FFh contains the MOVLW XX

INTERNAL RC oscillator calibra-

tion value.

512 Word

1024 Word

03FFh

0400h

On-chip Program

Memory

RFPIC12C509AF Datasheet(PDF) 17 Page - Microchip Technology

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