RFPIC12C509AF datasheet(52/104 Pages) MICROCHIP

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rfPIC12C509AG/509AF

DS70031A-page 50

Preliminary

FIGURE 8-9:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE

TIME

8.5

Device Reset Timer (DRT)

In the rfPIC12C509AG/509AF, DRT runs from RESET

and varies based on oscillator selection (see Table 8-

5).

The DRT operates on an internal RC oscillator. The

processor is kept in RESET as long as the DRT is

active. The DRT delay allows VDD to rise above VDD

min., and for the oscillator to stabilize.

Oscillator circuits based on crystals or ceramic resona-

tors require a certain time after power-up to establish a

stable oscillation. The on-chip DRT keeps the device in

a RESET condition for approximately 18 ms after

MCLR has reached a logic high (VIHMCLR) level. Thus,

programming GP3/MCLR/VPP as MCLR and using an

external RC network connected to the MCLR input is

not required in most cases, allowing for savings in cost-

sensitive and/or space restricted applications, as well

as allowing the use of the GP3/MCLR/VPP pin as a

general purpose input.

The Device Reset time delay will vary from chip to chip

due to VDD, temperature, and process variation. See

AC parameters for details.

The DRT will also be triggered upon a Watchdog Timer

time-out. This is particularly important for applications

using the WDT to wake from SLEEP mode automati-

cally.

8.6

Watchdog Timer (WDT)

The rfPIC12C509AG/509AF has a Watchdog Timer

which can be shut off only through configuration bit

WDTE. It runs off of its own RC oscillator for added reli-

ability. If using XT or LP selectable oscillator options,

there is always an 18 ms (nominal) delay provided by

the Device Reset Timer (DRT), intended to keep the

chip in RESET until the crystal oscillator is stable. If

using INTRC or EXTRC there is an 18 ms delay only on

VDD power-up. With this timer on-chip, most applica-

tions need no external RESET circuitry.

The Watchdog Timer (WDT) is a free running on-chip

RC oscillator which does not require any external com-

ponents. This RC oscillator is separate from the exter-

nal RC oscillator of the GP5/OSC1/CLKIN pin and the

internal 4 MHz oscillator. That means that the WDT will

run even if the main processor clock has been stopped,

for example, by execution of a SLEEP instruction. Dur-

ing normal operation or SLEEP, a WDT Reset or wake-

up Reset generates a device RESET.

The TO bit (STATUS<4>) will be cleared upon a Watch-

dog Timer Reset.

The WDT can be permanently disabled by program-

ming the configuration bit WDTE as a '0' (Section 8.1).

Refer to the PIC12C5XX Programming Specifications

to determine how to access the configuration word.

TABLE 8-5:

DRT (DEVICE RESET TIMER

PERIOD)

VDD

MCLR

INTERNAL POR

DRT TIME-OUT

INTERNAL RESET

TDRT

When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final

value. In this example, the chip will RESET properly if, and only if, V1

≥ VDD min.

Oscillator

Configuration

POR Reset

Subsequent

RESETS

IntRC &

ExtRC

18 ms (typical)

300 µs (typical)

XT & LP

18 ms (typical)

RFPIC12C509AF Datasheet(PDF) 52 Page - Microchip Technology

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