RFPIC12C509AF datasheet(39/104 Pages) MICROCHIP

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Preliminary

DS70031A-page 37

rfPIC12C509AG/509AF

7.4

Clock Output (CLKOUT)

The crystal oscillator feeds a divide-by-four circuit that

provides a clock output at the CLKOUT pin. The CLK-

OUT signal can be used as an input to the microcon-

troller or other external circuitry requiring a stable

reference frequency. Do not connect the CLKOUT sig-

nal to the PICmicro OSC1 input because the PICmicro

cannot run when there is no clock signal and therefore

cannot enable the transmitter oscillator. It is required

that the PICmicro be clocked externally or via the inter-

nal RC oscillator (see Section 8.2).

Connect CLKOUT to GP2/T0CKI input and use the

Timer0 module if the application requires a stable refer-

ence frequency.

CLKOUT is slew-rate limited in order to keep spurious

signal emissions as low as possible. The voltage swing

(VCLKOUT) depends on the capacitive loading (CLOAD)

on the CLKOUT pin (2 VPP at 5 pF).

7.5

Phase-Locked Loop (PLL)

The PLL consists of a phase-frequency detector (PFD),

charge pump, voltage-controlled oscillator (VCO), and

fixed divide-by-32 divider. An external loop filter is con-

nected to pin LF. The loop filter controls the dynamic

behavior of the PLL, primarily lock time and spur levels.

The application determines the loop filter requirements.

The rfPIC

™ employs a charge pump PLL that offers

many advantages over the classical voltage phase

detector PLL: infinite pull-in range and zero steady

state phase error. The charge pump PLL allows the

use of passive loop filters that are lower cost and mini-

mize noise. Charge pump PLLs have reduced flicker

noise thus limiting phase noise. Many of the classical

texts on PLLs do not cover this type of PLL, however,

today this is the most common type of PLL. This data

sheet briefly covers the general terms and design

requirements for the rfPIC. Detailed PLL design and

operation is beyond the scope of this data sheet. For

more information, the designer is referred to "

PLL Per-

formance, Simulation, and Design," Second Edition by

Dean Banerjee ISBN 0970820704. Banerjee covers

charge pump PLLs and loop filter selection.

The loop filter has a major impact on lock time and spur

levels. Lock time is the time it takes the PLL to lock on

frequency.

When the PLL is first powered on or is

changing frequencies, no data can be transmitted.

Lock time must be considered before data transmission

can begin. In addition to PLL lock time, the designer

must take into account the crystal oscillator start time of

approximately 1 ms. See Section 7.3 for more informa-

tion about the crystal oscillator. Reference spurs occur

at the carrier frequency plus and minus integer multi-

ples of the reference frequency. Phase noise refers to

noise generated by the PLL. Spur levels and phase

noise can increase the signal to noise ratio (SNR) of

the system and mask or degrade the transmitted sig-

nal.

The first order effect on PLL performance is loop band-

width.

Loop bandwidth (

c) is defined as the point

where the open loop phase transfer function equals 0

dB. Selecting a small loop bandwidth results in lower

spur levels but slower lock time. Selecting a larger loop

bandwidth results in a faster lock time but higher spur

levels.

Second order effects on PLL performance is Phase

margin (

φ)and Damping factor(ζ). Phase margin is a

measure of PLL stability. Choosing a phase margin

that is too low will result in PLL instability. Choosing a

higher phase margin results in less ringing and faster

lock time at the expense of higher spur levels. Loop fil-

ters are typically designed for a total phase margin

between 30 and 70 degrees. The aim of the designer

is to choose a loop bandwidth and phase margin that

gives the fastest possible lock time and meets the spur

level requirements of the application.

Damping factor governs the second order transient

response that determines the shape of the exponential

envelope of the natural frequency.

The natural fre-

quency, also called ringing frequency, is the frequency

of the VCO steering voltage as the PLL settles. Lock

time is proportional to damping factor and inversely

proportional to loop bandwidth.

The application determines the loop filter component

requirements. For example, if the transmit frequency

selected is near band edges or restricted bands, spur

levels must be reduced to meet regulatory require-

ments. However, this will be at the expense of lock

time. For an FSK application, a larger damping factor

(

≅ 1.0) is desired so that there is less overshoot in the

keying of FSK. For an ASK application, a damping fac-

tor = 0.707 results in less settling time and near opti-

mum noise performance.

Figure 7-5 shows an example passive second order

loop filter circuit. Table 7-4 gives example loop filter

values for a crystal frequency of 13.56 MHz and trans-

mit frequency of 433.92 MHz.

Layout considerations - Shield each side of the clock

output trace with ground traces to isolate the CLK-

OUT signal and reduce coupling.

Layout considerations - Keep traces short and place

loop filter components as close as possible to the LF

pin.

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