DM562P
V.90 Integrated Data/ Fax/Voice/Speakerphone
Modem Device Single Chip with Memory Built in
6
Preliminary
Version: DM562P-DS-P02
February 28, 2001
according to the rising edge of SCLK. The MSB is
sent immediately after the falling edge of the
FR_SP1 signal.
49
47
49
47
CA16
CA17
O
Bank Switch Control:
These signals are used to switch external program
memory between banks.
CA16
CA17
Bank 0
0
0
Bank 1
1
0
Bank 2
0
1
Bank 3
1
1
51
T0
I
Controller Counter 0 Input
52
T1
I
Controller Counter 1 Input
57
/RI
I
Ring Signal Input
57
TxSCLK*2
I
TxDSP Interrupt 1 Input (PCI)
58
58
/DTR
I
DTR Input Pin (P1.1)
59
59
/OH
O
Hook Relay Control (P1.2)
60
60
/VOICE
O
Voice Relay Control. Modem Control Output
(memory map is bit 3 of DAA at memory address
D000H)
61-63
61-63
EEPROM 1-3
I/O
EEPROM Control Pins (P1.4-P1.6)
66
/LCS
I
Loop Current Detection. Modem Input Control:
This pin is mapped to bit0 of address D000H.
66
SCLK
I
Reference Clock For Serial Port 1 And Serial
Port 2 (PCI)
68
RXD
I
Controller Serial Port Data Input
69
TXD
O
Controller Serial Port Data Output
68
RD_SP2
I
Data Input Pin Of The Serial Port 2 (PCI)
The serial data is sampled at the falling edge of the
SCLK. The MSB is coming immediately after the
falling of FR_SP2 signal.
69
RD_SP1
I
Data Input Pin Of The Serial Port 1 (PCI)
The serial data is sampled at the falling edge of the
SCLK. The MSB is coming immediately after the
falling of FR_SP1 signal.
70
70
RxSCLK
I
Rx DSP Interrupt 3 Input
71
71
/PSEN
O
Controller Program Store Enable:
This output goes low during a fetch from external
program memory.
72
72
/WR
O
Controller External Data Memory Write Control
73
73
/RD
O
Controller External Data Memory Read Control
76
TxSCLK*2
I
TxDSP Interrupt 3 Input (External)
78
DSPRxD
O
Modem Received Data (External)
Shifted out to the EIA port through this pin
according to the rising edge of RXDCLK.
79
SCLK
I
Reference Clock For Serial Port 1 And Serial
Port 2 (External)
117
117
TEST1
Test pin 1, normal ground
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