DM562P datasheet(8/43 Pages) ETC1

8 / 43 page

DM562P

V.90 Integrated Data/ Fax/Voice/Speakerphone

Modem Device Single Chip with Memory Built in

Preliminary

Version: DM562P-DS-P02

February 28, 2001

For the accesses to the configuration address space, the device select

decoding is done externally and is signaled via this pin. This signal is

asserted high during configuration read and write access.

C/BE3#

C/BE2#

C/BE1#

C/BE0#

PCI Bus Command/Byte Enable

During the address phase, these signals define the bus command or

the type of the bus transaction that will take place.

During the data phase, these pins indicate which byte lanes contain

valid data. C/BE0# applies to bit7~0 and C/BE3# applies to bit 31~24.

FRAME#

PCI Cycle Frame

This signal is driven low by the master to indicate the beginning and

duration of a bus transaction. It is deasserted when the transaction is

in its final phase.

IRDY#

PCI Initiator Ready

This signal is driven low when the master is ready to complete the

current data phase of the transaction. A data phase is completed on

any clock both IRDY# and TRDY# are sampled asserted.

TRDY#

I/O

PCI Target Ready

This signal is driven low when the target is ready to complete the

current data phase of the transaction. During a read, it indicates that

the valid data is asserted. During write, it indicates that the target

prepares to accept data.

DEVSEL#

I/O

PCI Device Select

DM6585 asserts the signal low when it recognizes its target address

after FRAME# is asserted.

STOP#

I/O

PCI Stop

This signal is asserted low by the target device to request the master

device to stop the current transaction.

PERR#

I/O

PCI Parity Error

DM6585 will assert this signal low to indicate a parity error on any

incoming data.

SERR#

PCI System Error

This signal is asserted low when an address parity is detected with

PCICS bit31 enabled. The system error asserts two clock cycles after

the address if an address parity error is detected.

PAR

I/O

PCI Parity

This signal indicates even parity across AD0~AD31 and

C/BE0#~C/BE3# including the PAR pin. It is stable and valid one clock

after the address phase.

RST#

Reset:

An active low signal used to reset the DM6588.

VCC_AUX

+3.3V Auxiliary Power Supply

RIN

Ring Signal Input for Auxiliary Power

GND_AUX

Auxiliary Ground

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