GD25Q256DFER datasheet(2/89 Pages) GIGADEVICE

2 / 89 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q256D

Contents

FEATURES ..................................................................................................................................................4

GENERAL DESCRIPTION ..........................................................................................................................5

MEMORY ORGANIZATION.........................................................................................................................8

DEVICE OPERATION ..................................................................................................................................9

DATA PROTECTION ................................................................................................................................. 11

STATUS AND EXTENDED ADDRESS REGISTERS................................................................................12

6.1.

STATUS REGISTERS ..............................................................................................................................12

6.2.

EXTENDED ADDRESS REGISTER ............................................................................................................16

COMMANDS DESCRIPTION ....................................................................................................................17

7.1.

WRITE ENABLE (WREN) (06H) .............................................................................................................22

7.2.

WRITE DISABLE (WRDI) (04H)..............................................................................................................22

7.3.

WRITE ENABLE FOR VOLATILE STATUS REGISTER (50H) ........................................................................23

7.4.

READ STATUS REGISTER (RDSR) (05H OR 35H OR 15H) ......................................................................23

7.5.

WRITE STATUS REGISTER (WRSR) (01H OR 31H OR 11H)....................................................................24

7.6.

READ EXTENDED REGISTER (C8H)........................................................................................................25

7.7.

WRITE EXTENDED REGISTER (C5H) ......................................................................................................25

7.8.

READ DATA BYTES (READ 03H OR 4READ 13H) .................................................................................26

7.9.

READ DATA BYTES AT HIGHER SPEED (FAST READ 0BH OR 4FAST READ 0CH)......................................27

7.10.

DUAL OUTPUT FAST READ (DOFR 3BH OR 4DOFR 3CH).....................................................................28

7.11.

QUAD OUTPUT FAST READ (QOFR 6BH OR 4QOFR 6CH)....................................................................30

7.12.

DUAL I/O FAST READ (DIOFR BBH OR 4DIOFR BCH)..........................................................................32

7.13.

QUAD I/O FAST READ (QIOFR EBH OR 4QIOFR ECH).........................................................................36

7.14.

SET BURST WITH WRAP (77H) ..............................................................................................................39

7.15.

PAGE PROGRAM (PP 02H OR 4PP 12H) ...............................................................................................39

7.16.

QUAD PAGE PROGRAM (QPP 32H OR 4QPP 34H) ................................................................................42

7.17.

SECTOR ERASE (SE 20H OR 4SE 21H).................................................................................................45

7.18.

32KB BLOCK ERASE (BE32 52H OR 4BE32 5CH) ................................................................................46

7.19.

64KB BLOCK ERASE (BE64 D8H OR 4BE64 DCH) ...............................................................................47

7.20.

CHIP ERASE (CE) (60/C7H)..................................................................................................................48

7.21.

DEEP POWER-DOWN (DP) (B9H) ..........................................................................................................48

7.22.

READ UNIQUE ID (4BH) ........................................................................................................................49

7.23.

ENTER 4-BYTE ADDRESS MODE (B7H) ..................................................................................................50

7.24.

EXIT 4-BYTE ADDRESS MODE (E9H) .....................................................................................................50

7.25.

CLEAR SR FLAGS (30H) .......................................................................................................................51

7.26.

RELEASE FROM DEEP POWER-DOWN AND READ DEVICE ID (RDI) (ABH) ...............................................51

7.27.

READ MANUFACTURE ID/ DEVICE ID (REMS) (90H) ..............................................................................52

7.28.

READ MANUFACTURE ID/ DEVICE ID DUAL I/O (92H) .............................................................................53

7.29.

READ MANUFACTURE ID/ DEVICE ID QUAD I/O (94H).............................................................................54

7.30.

READ IDENTIFICATION (RDID) (9FH) .....................................................................................................55

GD25Q256DFER Datasheet(PDF) 2 Page - GigaDevice Semiconductor (Beijing) Inc.

GD25Q256DFER Datasheet(HTML) 2 Page - GigaDevice Semiconductor (Beijing) Inc.

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