GD25Q256DFER datasheet(40/89 Pages) GIGADEVICE

40 / 89 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q256D

As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page

Program cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The

Write in Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified

time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.

A Page Program (PP) command applied to a page which is protected by the Block Protect (TB, BP3, BP2, BP1, and

BP0) is not executed.

Figure 37. Page Program Sequence Diagram (ADS=0)

Figure 38. Page Program Sequence Diagram (ADS=1)

Command

02H

CS#

SCLK

9 10

28 29 30 31

23 22 21

24-bit address

42 43 44 45

46 47

50 51 52 53

54 55

CS#

SCLK

MSB

Data Byte 2

32 33 34 35

MSB

Data Byte 1

Data Byte 3

Data Byte 256

MSB

36 37 38 39

Command

02H

CS#

SCLK

9 10

36 37 38 39

31 30 29

32-bit address

58 59 60 61

62 63

CS#

SCLK

MSB

Data Byte 2

MSB

Data Byte 1

Data Byte 3

Data Byte 256

MSB

42 43 44 45

46 47

50 51 52 53

54 55

GD25Q256DFER Datasheet(PDF) 40 Page - GigaDevice Semiconductor (Beijing) Inc.

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