GD25Q256DFER datasheet(25/89 Pages) GIGADEVICE

25 / 89 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q256D

7.6.

Read Extended Register (C8H)

Extended Register contains Address Bit A24. The Read Extended Register instruction is entered by driving CS# low

and shifting the instruction code “C8H” into the SI pin on the rising edge of SCLK. The Extended Register bits are then

shifted out on the SO pin at the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 10.

When the device is in the 4-Byte Address Mode, the value of A24 Bit is ignored.

Figure 10 Read Extended Register Sequence Diagram

7.7.

Write Extended Register (C5H)

The Write Extended Register command could be executed no matter the Write Enable Latch (WEL) bit is 0 or 1.The

Write Extended Register instruction is entered by driving CS# low,

sending the instruction code “C5H”, and then writing the

Extended Register data Byte as illustrated in Figure 11.

Upon power up or the execution of a Software/Hardware Reset, the Extended Register bit values will be cleared to 0.

Figure 11 Write Extended Register Sequence Diagram

Command

C8H

CS#

SCLK

High-Z

9 10 11 12 13 14 15

MSB

Extended Addr.

MSB

Extended Addr.

Command

C5H

CS#

SCLK

High-Z

9 10 11 12 13 14 15

MSB

Extended Addr.

GD25Q256DFER Datasheet(PDF) 25 Page - GigaDevice Semiconductor (Beijing) Inc.