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GD25Q256DFER Datasheet(PDF) 4 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25Q256DFER Datasheet(HTML) 4 Page - GigaDevice Semiconductor (Beijing) Inc. |
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4 / 89 page ![]() 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D 4 1. FEATURES ◆ 256M-bit Serial Flash ◆ Fast Program/Erase Speed - 256 Bytes per programmable page -Page Program time: 0.4ms typical -Sector Erase time: 70ms typical ◆ Standard, Dual, Quad SPI -Block Erase time: 0.16/0.22s typical - Standard SPI: SCLK, CS#, SI, SO,WP#, HOLD#/RESET# -Chip Erase time: 70s typical - Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#/RESET# - Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3 ◆ Flexible Architecture - 3 or 4-Byte Addressing Mode -Uniform Sectors of 4K-Byte -Uniform Blocks of 32/64K-Byte ◆ High Speed Clock Frequency -Maximum 104MHz for fast read on 3.0 - 3.6V power supply ◆ Low Power Consumption ◆ Dual I/O Data transfer up to 208Mbits/s - 1uA typical deep power down current ◆ Quad I/O Data transfer up to 416Mbits/s - 12uA typical standby current -Maximum 80MHz for fast read on 2.7 - 3.6V power supply ◆ Dual I/O Data transfer up to 160Mbits/s ◆ Quad I/O Data transfer up to 320Mbits/s ◆ Advanced Security Features -3*2048-Byte Security Registers With OTP Locks ◆ Software Write Protection -128-bit Unique ID -Write protect all/portion of memory via software -Serial Flash Discoverable parameters (SFDP) register -Top/Bottom Block protection ◆ Single Power Supply Voltage ◆ Allows XIP(execute in place) Operation -Full voltage range:2.7 - 3.6V -Continuous Read With 8/16/32/64-Byte Wrap ◆ Package Information ◆ Cycling Endurance and Data Retention -SOP16 (300mil) -Minimum 100,000 Program/Erase Cycles -WSON8 (8*6mm) -20-year data retention typical -TFBGA-24 (5*5 ball array) |
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