GD25Q256DFER datasheet(60/89 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q256D

7.35.

Read Security Registers (48H)

The Read Security Registers command is similar to Fast Read command. The command i is followed by a 3-Byte

address (A23-A0) or 4-Byte address (A31-A0) and a dummy Byte, and each bit being latched-in on the rising edge of SCLK.

Then the memory content, at that address, is shifted out on SO, and each bit being shifted out, at a Max frequency fC, on

the falling edge of SCLK. The first Byte addressed can be at any location. The address is automatically incremented to the

next higher address after each Byte of data is shifted out. Once the A10-A0 address reaches the last Byte of the register

(Byte 7FFH), it will reset to 000H, the command is completed by driving CS# high.

Table 20. Security Registers

Address

A23-16

A15-12

A11

A10-0

Security Register #1

00H

0 0 0 1

Byte Address

Security Register #2

00H

0 0 1 0

Byte Address

Security Register #3

00H

0 0 1 1

Byte Address

Figure 71. Read Security Registers command Sequence Diagram (ADS=0)

Figure 72. Read Security Registers command Sequence Diagram (ADS=1)

Command

48H

CS#

SCLK

High-Z

9 10

28 29 30 31

23 22 21

24-bit address

MSB

34 35 36 37

38 39

Data Out1

42 43 44 45

46 47

Data Out2

CS#

SCLK

MSB

Dummy Byte

Command

48H

CS#

SCLK

High-Z

9 10

36 37 38 39

31 30 29

32-bit address

MSB

Data Out1

50 51 52 53

54 55

Data Out2

CS#

SCLK

MSB

Dummy Byte

42 43 44 45

46 47

GD25Q256DFER Datasheet(PDF) 60 Page - GigaDevice Semiconductor (Beijing) Inc.

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