GD25Q256DFER datasheet(22/89 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q256D

7.1. Write Enable (WREN) (06H)

The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL)

bit must be set prior to every Page Program (PP), Quad Page Program (QPP), Sector Erase (SE), Block Erase (BE), Chip

Erase (CE), Write Status Register (WRSR). The Write Enable (WREN) command sequence: CS# goes low  sending the

Write Enable command  CS# goes high.

Figure 5. Write Enable Sequence Diagram

7.2. Write Disable (WRDI) (04H)

The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit may

be set to a 0 by issuing the Write Disable (WRDI) command to disable Page Program (PP), Quad Page Program (QPP),

Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status Register (WRSR), that require WEL be set to 1 for

execution. The WRDI command can be used by the user to protect memory areas against inadvertent writes that can

possibly corrupt the contents of the memory. The WRDI command is ignored during an embedded operation while WIP bit

=1.

The WEL bit is reset by following condition: Write Disable command (WRDI), Power-up, and upon completion of the

Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase commands.

The Write Disable command sequence: CS# goes low Sending the Write Disable command CS# goes high.

Figure 6. Write Disable Sequence Diagram

Command

06H

CS#

SCLK

High-Z

Command

04H

CS#

SCLK

High-Z

GD25Q256DFER Datasheet(PDF) 22 Page - GigaDevice Semiconductor (Beijing) Inc.