GD25Q256DFER datasheet(32/89 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q256D

Figure 23.Fast Read Quad Output with 4-Byte Address Sequence Diagram (ADS=0 or ADS=1)

Note:

1. The dummy clock number is configurable.

7.12.

Dual I/O Fast Read (DIOFR BBH or 4DIOFR BCH)

The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input the

3-Byte address (A23-

0) and a “Continuous Read Mode” Byte 2-bit per clock by SI and SO, and each bit being latched in on

the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command

sequence is shown in followed Figure24. The first Byte addressed can be at any location. The address is automatically

incremented to the next higher address after each Byte of data is shifted out.

Dual I/O Fast Read with

“Continuous Read Mode”

The Dual I/O Fast Read command

can further reduce command overhead through setting the “Continuous Read Mode”

bits (M7-4) after the input 3-Byte address (A23-A0).

If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next Dual

I/O Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. The command

sequence is shown in followed Figure25.

If the “Continuous Read Mode” bits (M5-4) do not equal (1, 0), the next command

requires the command code, thus returning to normal operation. A Reset command can be used to reset (M5-4) before

issuing normal command.

Command

6CH

CS#

SCLK

SI(IO0)

SO(IO1)

High-Z

9 10

36 37 38 39

31 30 29

32-bit address

Byte1

Dummy Clocks

WP#(IO2)

High-Z

HOLD#(IO3)

High-Z

CS#

SCLK

SI(IO0)

SO(IO1)

WP#(IO2)

HOLD#(IO3)

Byte2 Byte3 Byte4

42 43 44 45

46 47

50 51 52 53

54 55

GD25Q256DFER Datasheet(PDF) 32 Page - GigaDevice Semiconductor (Beijing) Inc.

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