GD25Q256DFER datasheet(14/89 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q256D

LB3, LB2, LB1 bits.

The LB3, LB2, LB1 bits are non-volatile One Time Program (OTP) bits in Status Register (S13, S12, S11) that provide

the write protect control and status to the Security Registers. The default state of LB3-LB1 are 0, the security registers are

unlocked. The LB3-LB1 bits can be set to 1 individually using the Write Register instruction. The LB3-LB1 bits are One Time

Programmable, once they are set to 1, the Security Registers will become read-only permanently.

SUS1, SUS2 bit

The SUS1 and SUS2 bit are read only bit in the status register (S15 and S10) that are set to 1 after executing an

Program/Erase Suspend (75H) command (The Erase Suspend will set the SUS1 to 1,and the Program Suspend will set the

SUS2 to 1). The SUS1 and SUS2 bit are cleared to 0 by Program/Erase Resume (7AH) command, software reset (66H+99H)

command as well as a power-down, power-up cycle.

DRV1, DRV0 bits

The DRV1&DRV0 bits are used to determine the output driver strength for the Read operations.

Table 11. Driver Strength for Read Operations

DRV1,DRV0

Driver Strength

100%

75% (Default)

Reserved

HOLD/RST bit

The HOLD/RST bit is used to determine whether HOLD# or RESET# function should be implemented on the hardware

pin for 8-pin packages. When HOLD/RST=0, the pin acts as HOLD#, When the HOLD/RST=1, the pin acts as RESET#.

However, the HOLD# or RESET# function are only available when QE=0, If QE=1, The HOLD# and RESET# functions are

disabled, the pin acts as dedicated data I/O pin.

Reserved bit

It is recommended to set the value of the reserved bit

as “0”.

PE bit

The Program Error (PE) bit is a read only bit that indicates a program failure. It will also be set when the user attempts

to program a protected array sector or access the locked OTP space.

Error bits can be reset by CLEAR FLAG STATUS REGISTER command (30H).

EE bit

The Erase Error (EE) bit is a read only bit that indicates an erase failure. It will also be set when the user attempts to

erase a protected array sector or access the locked OTP space.

Error bits can be reset by CLEAR FLAG STATUS REGISTER command (30H).

ADS bit

The Address Status (ADS) bit is a read only bit that indicates the current address mode the device is operating in. The

device is in 3-Byte address mode when ADS=0 (default), and in 4-Byte address mode when ADS=1.

GD25Q256DFER Datasheet(PDF) 14 Page - GigaDevice Semiconductor (Beijing) Inc.