GD25Q256DFER datasheet(28/89 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q256D

Figure 17. Fast Read with 4-Byte Address Sequence Diagram (ADS=0 or ADS=1)

Note:

1. The dummy clock number is configurable.

7.10.

Dual Output Fast Read (DOFR 3BH or 4DOFR 3CH)

The Dual Output Fast Read command is followed by 3-Byte address (A23-A0) and a dummy Byte, and each bit being

latched in on the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO.

The command sequence is shown in followed Figure 18. The first Byte addressed can be at any location. The address is

automatically incremented to the next higher address after each Byte of data is shifted out.

Figure 18. Dual Output Fast Read Sequence Diagram (ADS=0)

Note:

1. The dummy clock number is configurable.

Command

3BH

CS#

SCLK

High-Z

9 10

28 29 30 31

23 22 21

24-bit address

MSB

34 35 36 37

38 39

Data Out1

42 43 44 45

46 47

Data Out2

CS#

SCLK

MSB

Dummy Clocks

Command

0CH

CS#

SCLK

High-Z

9 10

36 37 38 39

31 30 29

32-bit address

MSB

42 43 44 45

46 47

Data Out1

50 51 52 53

54 55

Data Out2

CS#

SCLK

MSB

Dummy Byte

GD25Q256DFER Datasheet(PDF) 28 Page - GigaDevice Semiconductor (Beijing) Inc.

GD25Q256DFER Datasheet(HTML) 28 Page - GigaDevice Semiconductor (Beijing) Inc.

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