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GD25Q256DFER Datasheet(PDF) 37 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25Q256DFER Datasheet(HTML) 37 Page - GigaDevice Semiconductor (Beijing) Inc. |
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37 / 89 page ![]() 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D 37 Figure 32. Quad I/O Fast Read Sequence Diagram (M5- 4≠ (1, 0), ADS=1) Note: 1. The dummy clock number is configurable. Figure 33.Quad I/O Fast Read Sequence Diagram (M5-4= (1, 0), ADS=1) Note: 1. The dummy clock number is configurable. Command 0 1 2 3 4 5 6 7 EBH CS# SCLK SI(IO0) SO(IO1) 8 9 10 11 12 13 14 15 4 0 4 0 4 0 4 0 16 17 18 19 20 21 22 23 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 A23-16A15-8 A7-0 M7-0 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 WP#(IO2) HOLD#(IO3) 4 5 6 7 Dummy Byte1 Byte2 4 0 5 1 6 2 7 3 A31-24 24 25 0 1 2 3 4 5 6 7 CS# SCLK 8 9 10 11 12 13 14 15 SI(IO0) SO(IO1) WP#(IO2) HOLD#(IO3) 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 5 6 7 A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 16 17 4 0 5 1 6 2 7 3 A31-24 |
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