ADF5610 datasheet(32/51 Pages) AD

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ADF5610

Data Sheet

Rev. 0 | Page 32 of 51

Then, for Channel 1,















VCO1

)

(

where fVCO1 = 2800.2 MHz.

The following equation provides the value for Register 0x04

for operating in Channel 1 (fVCO1 = 2800.2 MHz).

2 (2800.2 10

2764.8 10 )

ceil

9666560

61.44 10

0x938000

decimal

















To change from Channel 1 (fVCO1 = 2800.2 MHz) to

Channel 2 (fVCO2 = 2800.3 MHz), only Register 0x04 must

be programmed, as long as all of the desired exact

frequencies (fVCOk, see Figure 26) fall between the same

Integer N boundaries (fN < fVCOk < fN + 1). In that case,

2 (2800.3 10

2764.8 10 )

ceil

61.44 10

9693867

0x93EAAB

decimal

















Seed Register

The start phase of the fractional modulator digital phase

accumulator (DPA) can be set to one of four possible default

values via the SEED_SELECT bits, Register 0x06, Bits[1:0]. The

ADF5610 automatically reloads the start phase (seed value) into

the DPA every time a new fractional frequency is selected.

Certain zero seed values or binary seed values may cause

spurious energy correlation at specific frequencies. For most

cases, a random (not zero and not binary) start seed is

recommended (Register 0x06, Bits[1:0] = 2).

SOFT RESET AND POWER-ON RESET

The ADF5610 features a hardware power-on reset (POR). All

chip registers are reset to default states approximately 250 μs

after power-up.

The PLL subsystem SPI registers can also be soft reset by an SPI

write to Register 0x00. Note that the soft reset does not clear the

SPI mode of operation referred to in the SPI Modes of Operation

section. The VCO subsystem is not affected by the PLL soft reset.

The VCO subsystem registers can only be reset by removing the

power supply.

If external power supplies or regulators have rise times slower than

250 μs, write to the SPI RST_SWRST bit (Register 0x00, Bit 5 = 1)

immediately after power-up, before any other SPI activity. This

write procedure ensures starting from a known state.

POWER-DOWN MODE

The VCO subsystem is not affected by the CEN pin or PLL soft

reset. Therefore, device power-down consists of the following

two-step process:

Power down the VCO by writing 1 to VCO Register 0x02,

Bit 3 via PLL Register 0x05.

Power down the PLL by pulling the CEN pin (Pin 44) low

(assuming there are no SPI overrides (Register 0x01, Bit 0 =

1)). Pulling the CEN pin low disables all analog functions

and internal clocks. Current consumption typically drops

to 100 μA in the power-down state if the reference input is

disconnected. The serial port still responds to normal

communication in power-down mode.

It is possible to ignore the CEN pin by setting Register 0x01,

Bit 0 = 0. Control of the power-down mode then comes from

the serial port register, Register 0x01, Bit 1.

It is also possible to leave various blocks turned on when in

power-down (see Register 0x01), as listed in Table 12.

Table 12. Bit and Block Assignments for Register 0x01

Bit Assignment

Block Assignment

Bit 2

Internal bias reference sources

Bit 3

PD block

Bit 4

CP block

Bit 5

Reference path buffer

Bit 6

VCO path buffer

Bit 7

Digital I/O test pads (GPO driver)

GENERAL-PURPOSE OUTPUT (GPO)

The PLL shares the SDO (lock detect/serial data output) pin to

perform various functions. Although the pin is most commonly

used to read back registers from the chip via the SPI, the pin is

also capable of exporting a variety of signals and real-time test

waveforms (including lock detect). The SDO pin is driven by a

tristate CMOS driver with ~200 Ω ROUT. The SDO pin has logic

associated with it to dynamically select whether the driver is

enabled, and to determine which data to export from the chip.

In the default configuration of the output driver, after POR, the

output driver is disabled, and drives only during appropriately

addressed SPI reads. This configuration allows the ADF5610 to

share its output with other devices on the same bus.

The pin driver is enabled if the chip is addressed. That is, the

last three bits of the SPI cycle = 000b before the rising edge of

SEN. If SEN rises before SCK has clocked in an invalid (nonzero)

chip address, the ADF5610 starts to drive the bus.

To monitor any of the GPO signals, including lock detect, set

setting stops the LDO driver from tristating and means that the

SDO line cannot be shared with other devices.

The ADF5610 naturally switches from the GPO data and exports

the SDO signal during an SPI read. To prevent this automatic data

selection and to always select the GPO signal, set Register 0x0F,

Bit 6 = 1 to prevent automuxing of the SDO pin. The phase

noise performance at this output is poor and uncharacterized.

Also, do not toggle the GPO during normal operation because

toggling may degrade the spectral performance.

ADF5610 Datasheet(PDF) 32 Page - Analog Devices

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