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ADF5610 Datasheet(PDF) 49 Page - Analog Devices |
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ADF5610 Datasheet(HTML) 49 Page - Analog Devices |
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49 / 51 page ![]() Data Sheet ADF5610 Rev. 0 | Page 49 of 51 Example: Setting the Differential Output Divider to Divide by 64 via the VCO Subsystem The VCO registers are written in reverse order (highest to lowest). First, set the divide ratio then enable the divider. Finally, select the band. To write 0 0000 0001 into VCO Register 0x02 (VCO_ID = 000b) and set the VCO output divider to divide by 64, the following must be written to Register 0x05 = 0 0000 0001 0010 000 = 0x0090: • Register 0x05, Bits[2:0] = 000. 3-bit VCO_ID, target subsystem address = 000b. • Register 0x05, Bits[6:3] = 0010. VCO Register 0x02 address. • Register 0x05, Bits[16:7] = 0 0000 0001. Divide by 64, maximum output RF gain. Next, use the same settings for Bits[14:0] in the Example: Optimizing Power and Phase Noise Performance at RFOUT Using the VCO Subsystem section for VCO Register 0x01. To enable the differential output divider, simply change VCO Register 0x01, Bit 8 = 1. The full VCO subsystem write via PLL Register 0x05 = 0011111110001000 = 0xBF88. The following settings illustrate how settings for VCO Register 0x01 translate to Register 0x05. • Register 0x05, Bits[2:0] = 000b. 3-bit VCO_ID, target subsystem address = 000b. • Register 0x05, Bits[6:3] = 0001b. VCO subsystem register address. • Register 0x05, Bits[8:7] = 11b. RFOUT maximum output power, 5 dBm nominally. • Register 0x05, Bits[11:9] = 111b. VCO bias, high performance mode. • Register 0x05, Bits[13:12] = 11b. Divider output power, 3 dBm. • Register 0x05, Bit 14 = 0b. Reserved. • Register 0x05, Bit 15 = 1b. Enable differential output divider (note that RFOUT power level drops by ~1 dBm). If no VCO band change is required, register writes are complete. Example: Changing Frequency after Configuring the VCO If writing to the synthesizer for the first time or if the user is changing frequencies, a write to Register 0x05 = 0 to allow a subsequent frequency change via autocalibration is required. The last write in the PLL register sequence triggers the frequency update. If an integer value results at the phase detector input, the last write in the register sequence is PLL Register 0x03. If a fractional value results at the phase detector input, the last write in the register sequence is PLL Register 0x04. If the band for the desired RFOUT frequency (prior to division) is already known, the VCO band can be written to directly via VCO Register 0x00 by disabling the temperature controlled VT calibration voltage and manually selecting the band via VCO Register 0x00. For example, assume that the desired RFOUT frequency prior to division is 8 GHz and 8 GHz falls in Subband 205 (see Table 35) when autocalibration is used at room temperature. First, set VCO Register 0x02 = 0x0090 for divide by 64 and maximum output power at PDIV_OUT and NDIV_OUT. Next, set VCO Register 0x01 = 0xBF88 for maximum output power on the RFOUT port and the optimal phase noise performance on all ports. Lastly, configure the VCO Register 0x00 subsystem write via PLL Register 0x05 = 1100110100000000 = 0xCD00. The following are individual bit field settings used in Register 0x05 to achieve the write to VCO Register 0x00. • Register 0x05, Bits[2:0] = 000b. 3-bit VCO_ID, target subsystem address = 000b. • Register 0x05, Bits[6:3] = 0000b. VCO subsystem register address. • Register 0x05, Bit 7 = 0b. Disable autocalibration. • Register 0x05, Bits[15:8] = 1100101 (205 decimal). Subband 205 = Subband 77 of the lower VCO core (see Table 35). |
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