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Data Sheet

ADF5610

Rev. 0 | Page 17 of 51

SPI CONFIGURATION OF PLL AND VCO

SUBSYSTEMS

The two subsystems (PLL and VCO) each have their own

the VCO Subsystem Register Map section. Typically, writes to

both register maps are required for initialization and frequency

tuning operations.

As shown in Figure 18, the PLL subsystem is connected directly

to the SPI interface of the ADF5610, whereas VCO SPI commands

are passed through the PLL subsystem to the ADF5610 VCO. As

a result, writes to the PLL register map are written directly and

immediately, whereas the writes to the VCO subsystem register

map are written to PLL Register 0x05 and forwarded via the

internal VCO SPI (VSPI) to the VCO subsystem, which is a

form of indirect addressing.

The VCO registers are write only and cannot be read. However,

the VCO tuning band that is currently enabled can be read back

via PLL Register 0x0A. For more information, see the VCO

Serial Port Interface (VSPI) section.

VCO Serial Port Interface (VSPI)

The ADF5610 communicates with the internal VCO subsystem

via an internal 16-bit VSPI. The internal serial port controls the

step tuned VCO and other VCO subsystem functions.

The internal VSPI runs at the rate of the autocalibration FSM

clock (tFSM) (see the VCO Autocalibration section), where the

FSM clock frequency cannot be greater than 50 MHz. The VSPI

clock rate is set by PLL Register 0x0A, Bits[14:13].

Writes to the control registers of the VCO are handled indi-

rectly via writes to Register 0x05 of the ADF5610. A write to

packet, MSB first, across its internal serial link to the VCO

subsystem, where the packet is interpreted.

VSPI Use of Register 0x05

The packet data written into Register 0x05 is subparsed by logic

at the VCO subsystem into the following three fields:

•

Field 1, Bits[2:0]: 3-bit VCO_ID, target subsystem address =

000b.

•

Field 2, Bits[6:3]: 4-bit VCO_REGADDR, the internal

•

Field 3, Bits[15:7]: 9-bit VCO_DATA, the data field to

write to the VCO register.

For example, to write 0 0000 0110 into VCO Register 0x02 of

the VCO subsystem (VCO_ID = 000b) and set the VCO output

divider to divide by 2, the following must be written to

•

0b (VCO_DATA, Bit 15)

•

0000b (VCO_DATA, Bits[14:11])

•

0110b (VCO_DATA, Bits[10:7])

•

0010b (VCO_REGADDR)

•

000b (VCO_ID)

When concatenated, the result is Register 0x05 = 0x0310.

During autocalibration, the autocalibration controller writes

into the VCO register address specified by the VCO_ID and

VCO_REGADDR, as stored in Register 0x05, Bits[2:0] and

that the values for VCO_ID be zero (Register 0x05, Bits[2:0] =

0). When the VCO_ID values are not zero (Register 0x05,

Bits[2:0] ≠ 0), autocalibration does not function. Because VCO

frequencies, Register 0x05, Bits[6:0] = 0.

To ensure that frequency changes can occur after configuring the

VCO subsystem settings in Register 0x05, it is critical to write

but prior to the output frequency change. The frequency change

is triggered by the final PLL register write, which is Register 0x03

for integer values or Register 0x04 for fractional frequencies.

triggers autocalibration to implement a frequency change. When

operating in fractional mode, Register 0x04 is written last to trig-

ger autocalibration to make a frequency change. If the last write

to Register 0x05, Bits[6:0] ≠ 0), autocalibration does not function.

Note that it is impossible to write only Register 0x05, Bits[6:0] =

0 (VCO_ID and VCO_REGADDR) without also writing to

VCO_DATA (Register 0x05, Bits[15:7]). Therefore, if it is

desired to remain in the existing VCO band and only change

the divide ratio (see previous example), the user must ensure

that VCO_DATA (Register 0x05, Bits[15:7]) is not changed. To

accomplish this, it is required to read the band settings provided

in Register 0x10, Bits[7:0], and then rewrite them to Register 0x05,

Bits[15:7] as follows:

1. Read Register 0x10.

2. Write the following to Register 0x05:

a. Register 0x05, Bits[15:14] = Register 0x10, Bits[7:6].

b. Register 0x05, Bit 13 = 1 (reserved bit).

c. Register 0x05, Bits[12:8] = Register 0x10, Bits[4:0].

d. Register 0x05, Bits[7:0] = 0.

Changing the VCO subsystem configuration (see the VCO

Subsystem Register Map section) without following the preceding

procedure results in a failure to lock to the desired frequency.

For applications not using the read functionality of the ADF5610

SPI, in which Register 0x10 cannot be read, it is possible to write

sets the VCO subband setting equal to zero (Register 0x05,

Bits[15:7] = 0), effectively programming an incorrect VCO

subband settings and causing the ADF5610 to lose lock. This

procedure is then immediately followed by a write to the following:

•

This write effectively retriggers the FSM, forcing the ADF5610

to relock whether in integer mode or fractional mode.

ADF5610 Datasheet(PDF) 17 Page - Analog Devices

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