ADF5610

Data Sheet

Rev. 0 | Page 8 of 51

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

Floor Integer Mode

−229

dBc/Hz

Integer Mode

−232

dBc/Hz

Floor Fractional Mode

−226

dBc/Hz

Floor High Current Mode

Fractional Mode

−229

dBc/Hz

Flicker Noise (Integer

Mode and Fractional

Mode)

−268

dBc/Hz

Integrated RMS Jitter

<40

fs

VCO CHARACTERISTICS

VCO Tuning Sensitivity at

RFOUT

Measured on RFOUT (VT = 1.65 V)

7300 MHz

101

MHz/V

9000 MHz

80

MHz/V

11000 MHz

128

MHz/V

13000 MHz

109

MHz/V

14600 MHz

96

MHz/V

Tune Port Capacitance

VT = 0.5 V dc

175

pF

VT = 1.65 V dc

154

pF

VT = 2.8 V dc

135

pF

Autocalibration Delay

(Enable or Disable)

VCO Register 0x00, Bit 0 switch time (VT to

VPRST)

10

ns

VCO OUTPUT DIVIDER

VCO RF Divider Range

1, 2, 4, 6, 8, … 128

1

128

VCO Supply Pushing

PDIV_OUT and NDIV_OUT, divide by 1, VT =

1.65 V

0.7

MHz/V

VCO Supply Pushing

PDIV_OUT and NDIV_OUT, divide by 1, VT =

1.65 V

67

MHz/V

RETURN LOSS

RFOUT

5

dB

PDIV_OUT (N > 1)

14

dB

NDIV_OUT (N > 1)

14

dB

1

Pushing refers to a change in VCO frequency due to a change in the power supply voltage. To derive pushing at other divide ratios, divide the nominal pushing value

by the divide ratio.

2

Pulling refers to a change in VCO frequency due to a change in the load impedance.

3

Measured with 100 Ω external termination. See the Reference Input Stage section for more details.

4

Slew rate of ≥0.5 ns/V is recommended. See the Reference Input Stage section for more details. Frequency is guaranteed across process voltage and temperature from

−40°C to +85°C.

5

This maximum PD frequency can only be achieved if the minimum N value is respected. For example, in the case of fractional mode, the maximum PD frequency =

6

External 1 kΩ pull-up resistor to 1.8 V.

7

8

10 pF load capacitor.

9

10

1 kΩ pull-up resistor.

11

The minimum resistive load to ground in CMOS mode is 1 kΩ.

12

The SDO pin does not have short-circuit protection. Do not exceed the maximum current of 7.2 mA under any condition.

13

14

Values shown are the product of the prescaler divide ratio × N counter value.

15

VCCPD and VDDLS can be operated at 3.6 V maximum to increase band and VCO core overlap and extend the upper end of the frequency range. The typical current is

expected to be less than 1.5 mA. Both must be equal. Therefore, if one changes, so must the other. Exceeding 3.6 V results in ESD diodes drawing current.

16

Reference disconnected.

17

Some circuits remain on.

18

High current mode is a register setting that is enabled and works in conjunction with the functional mode in which the device is operating (integer mode or fractional

mode).