ADF5610 datasheet(28/51 Pages) AD

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ADF5610

Data Sheet

Rev. 0 | Page 28 of 51

Configuring the SDO Pin for LD Output

Setting Register 0x0F, Bit 7 = 1 and Register 0x0F, Bits[4:0] = 1

displays the lock detect flag on the SDO pin of the ADF5610.

When locked, SDO is high. As the name suggests, the SDO pin

is multiplexed between the LD and the serial data output (SDO)

signals. Therefore, LD is available on the SDO pin at all times

except when a serial port read is requested, in which case the

pin reverts temporarily to the serial data output pin and returns

to the lock detect flag after the read is completed.

LD can be made available on the SDO pin at all times by writing

provide any readback functionality because the SDO signal is

not available.

Cycle Slip Prevention (CSP)

When changing the VCO frequency and the VCO is not yet

locked to the reference, the instantaneous frequencies of the two

PD inputs are different, and the phase difference of the two

inputs at the PD varies rapidly over a range much greater than

±2π radians. Because the gain of the PD varies linearly with

phase up to ±2π, the gain of a conventional PD cycles from high

gain, when the phase difference approaches a multiple of 2π, to

low gain, when the phase difference is slightly larger than a

multiple of 0 radians. The output current from the charge pump

cycles from maximum to minimum, even though the VCO has

not yet reached its final frequency.

The charge on the loop filter small capacitor may actually

discharge slightly during the low gain portion of the cycle. This

discharge can make the VCO frequency reverse temporarily

during locking. This phenomenon is known as cycle slipping.

Cycle slipping causes the pull in rate during the locking phase

to vary cyclically. Cycle slipping increases the time to lock to a

value greater than predicted by normal small signal Laplace

transform analysis.

The ADF5610 PD features an ability to reduce cycle slipping

during acquisition. The CSP feature increases the PD gain

during large phase errors. The specific phase error that triggers

the momentary increase in PD gain is set via Register 0x0B,

Bits[8:7].

Frequency Tuning

The ADF5610 VCO subsystem always operates in the doubled

frequency range of operation (7300 MHz to 14600 MHz), which

is always available at the RFOUT port or at the differential

divider ports, PDIV_OUT and NDIV_OUT, when the divider is

set to divide by 1 in VCO Register 0x02, Bits[2:0].

Frequencies at or below the VCO fundamental frequency of

operation (57 MHz to 7300 MHz) are realized by tuning to the

appropriate doubled frequency and selecting the appropriate

output divider setting (divide by 2 to 128) in VCO Register 0x02,

Bits[2:0].

The fundamental band of operation (3650 MHz to 7300 MHz)

is input to the internal PLL and is not directly available to the

user. For more information, see the VCO Autocalibration section.

Integer Mode

The ADF5610 is capable of operating in integer mode. For

integer mode, set the following registers:

•

Disable the fractional modulator, Register 0x06, Bit 11 = 0

•

Bypass the modulator circuit, Register 0x06, Bit 7 = 1

In integer mode, the VCO step size is fixed to that of the PD

frequency. Integer mode typically has a 3 dB lower phase noise

than fractional mode for a given PD operating frequency. Integer

mode, however, often requires a lower PD frequency to meet

step size requirements. The fractional mode advantage is that

higher PD frequencies can be used. Therefore, lower phase

noise can often be realized in fractional mode. Disable the

charge pump offset when in integer mode.

Integer Frequency Tuning

In integer mode, the digital Σ-Δ modulator is shut off and the

N divider (Register 0x03) can be programmed to any integer

value in the range of 16 to 219 − 1. To run in integer mode,

configure Register 0x06 (as described in the Configuring the

SDO Pin for LD Output section), then program the integer

portion of the frequency as explained by Equation 12, ignoring

the fractional part.

The following sequence illustrates how to reconfigure the PLL

registers to switch from fractional mode to integer mode and

enable the output divider at the PDIV_OUT and NDIV_OUT

pins.

1. Disable the fractional modulator, Register 0x06, Bit 11 = 0.

2. Bypass the Δ-Σ modulator, Register 0x06, Bit 7 = 1.

3. Because the fundamental frequency (3650 MHz to

7300 MHz) range is supplied to the PLL, the fundamental

frequency is the basis for all programming. Determine the

fundamental frequency being used during operation.

4. If the fundamental frequency is <4000 MHz (RFOUT <

8000 MHz), set the internal prescaler to divide by 1

(Register 0x08, Bit 19 = 0). Otherwise, set the internal

prescaler to 1.

5. To tune to frequencies (<7300 MHz), select the appropriate

output divider value (VCO Register 0x02, Bits[2:0]), then

enable the differential output divider (VCO Register 0x01,

Bit 8 = 1).

Writing to the VCO subsystem registers (VCO Register 0x02,

Bits[2:0] and VCO Register 0x01, Bit 8 in this case) is

accomplished indirectly through PLL Register 0x05. For more

information on communicating with the VCO subsystem

through PLL Register 0x05, see the VCO Serial Port Interface

(VSPI) section.

ADF5610 Datasheet(PDF) 28 Page - Analog Devices

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