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ADF5610

Data Sheet

Rev. 0 | Page 16 of 51

THEORY OF OPERATION

NDIV_OUT

PDIV_OUT

RFOUT

DIVIDER

BUFFER

VCO BUFER

RFOUT PWR CNTL

DIV PWR CNTL

PLL BUFF

VSPI

CAL

CONTROL

MODULATOR

CHARGE

PUMP

PHASE

FREQUENCY

DETECTOP

DIVIDER

PLL ONLY

XREFP

CEN

SEN

SDI

SCK

SDO

DIVIDER

DIVIDER EN

VT SELECT

VCO EN

BIAS CNTL

VCO EN

DIVIDER

÷1, ÷2, ÷4, ÷8, ÷16,

÷32, ÷64, ÷128

Figure 18. PLL and VCO Subsystems

The ADF5610 PLL with integrated VCO is composed of two

subsystems, a PLL subsystem and a VCO subsystem, as shown

in Figure 18.

PLL SUBSYSTEM OVERVIEW

The PLL subsystem divides down the VCO output to the desired

comparison frequency via the N divider (integer value set in

the divided VCO signal to the divided reference signal (reference

divider set in Register 0x02) in the phase detector (PD), and

drives the VCO tuning voltage via the charge pump (CP)

(configured in Register 0x09) to the VCO subsystem. Some of

the additional PLL subsystem functions include



Δ-Σ configuration (Register 0x06).



Exact frequency mode (configured in Register 0x0C,



LD configuration (use Register 0x07 to configure LD and



External CEN pin used for the hardware PLL enable pin.

The CEN pin does not affect the VCO subsystem.

Only writes to the divider registers of the PLL subsystem are

required for ADF5610 output frequency changes.

The divider registers of the PLL subsystem (Register 0x03 and

7300 MHz) of the VCO subsystem. Output frequencies ranging

from 57 MHz to 14,600 MHz are generated by tuning to the

appropriate fundamental VCO frequency (3650 MHz to

7300 MHz), by programming the N divider (Register 0x03 and

1 to 128, in VCO Register 0x02) in the VCO subsystem.

Depending on the step size, high performance applications may

require one or more additional register writes to optimize spurs,

loop bandwidth and settling time, or to set the lock detect

window at the new frequency.

For detailed frequency tuning information and an example, see

the Frequency Tuning section.

VCO SUBSYSTEM OVERVIEW

The VCO subsystem consists of a switched capacitor, step tuned

VCO, and an output stage. The topology of the VCO allows both

fundamental and doubled frequency outputs. This arrangement

allows the lower, fundamental frequency of the oscillator to be

routed to the input of the PLL, which reduces the N counter of

the PLL by a factor of 2. This reduction of the N counter results

in not only a 3 dB improvement in the close in-phase noise, but

also prevents residual phase noise degradation at offsets beyond

10 MHz.

The VCO tuning is a two-step process consisting of a coarse then

fine tune. During normal operation, autocalibration is enabled

(Register 0x0A, Bit 11), which allows the PLL finite state

machine (FSM) to perform a binary search of the VCO bands

(coarse tune). After the proper band is located, the charge pump

output from the PLL takes control of the tuning port (VT) on

the VCO and adjusts to the proper fundamental frequency

(3650 MHz to 7300 MHz), and is phase locked by the PLL.

The VCO subsystem controls the output stages of the ADF5610,

enabling configuration of the following:



User defined performance settings (see the Programmable

Performance Technology section) that are configured via

VCO Register 0x01, Bits[4:2].



VCO output divider settings that are configured in VCO

frequencies from 3650 MHz to 57 MHz, respectively) or

divide by 1 to generate frequencies between 7300 MHz and

14,600 MHz.



RFOUT gain settings (VCO Register 0x01, Bits[1:0]).



PDIV_OUT and NDIV_OUT gain settings (VCO



Power down VCO (VCO Register 0x02, Bit 3).



Power down divider (VCO Register 0x01, Bit 8).

ADF5610 Datasheet(PDF) 16 Page - Analog Devices

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