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ADF5610 Datasheet(PDF) 39 Page - Analog Devices |
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ADF5610 Datasheet(HTML) 39 Page - Analog Devices |
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39 / 51 page  Data Sheet ADF5610 Rev. 0 | Page 39 of 51 PLL REGISTER MAP ID REGISTER, RESET STROBE REGISTER, AND OPEN MODE READ REGISTER The ID register is read only and returns the chip ID when read. The reset strobe register only contains one functional bit field for resetting all digital content and registers to the default values. The reset strobe register is write only. Table 15. Register 0x00, ID Register (Read Only) Bits Type Name Default Description 23:0 Read CHIP_ID A7975 ADF5610 chip ID Table 16. Register 0x00, Reset Strobe Register (Write Only) Bits Type Name Default Description 4:0 Write Reserved Not Applicable Reserved. Set all bits to 0 for proper operation. 5 Write RST_SWRST Not Applicable Strobe generates soft reset. Resets all registers to the default state. Can be used in both legacy mode and open mode. 23:6 Write Reserved Not Applicable Reserved. Set all bits to 0 for proper operation. Table 17. Register 0x00, Open Mode Read Address Register (Write Only) Bits Type Name Default Description 4:0 Write OPEN_MODE_READ_ADDRESS Not applicable Read address for next cycle when in open mode, two-cycle read. 5 Write RST_SWRST Not Applicable Strobe generates soft reset. Resets all registers to the default state. 23:6 Write Reserved Not applicable Reserved. Set all bits to 0 for proper operation. RST REGISTER Table 18. Register 0x01, RST Register (Default 0x000002) Bits Type Name Default Description 0 Read/Write RST_CHIPEN_PIN_SELECT 0 1 = power down the PLL via the CEN pin (see the Power-Down Mode section). 0 = power down the PLL via the SPI (RST_CHIPEN_FROM_SPI), Register 0x01, Bit 1. 1 Read/Write RST_CHIPEN_FROM_SPI 1 PLL enable bit of the SPI. 2 Read/Write KEEP_BIAS_ON 0 Keeps internal bias generators on, ignores chip enable control. 3 Read/Write KEEP_PFD_ON 0 Keeps PFD circuit on, ignores chip enable control. 4 Read/Write KEEP_CP_ON 0 Keeps charge pump on, ignores chip enable control. 5 Read/Write KEEP_REF_BUF_ON 0 Keeps reference buffer block on, ignores chip enable control. 6 Read/Write KEEP_VCO_BUF_ON 0 Keeps VCO divider buffer block on, ignores chip enable control. 7 Read/Write KEEP_GPO_DRIVER_ON 0 Keeps GPO output driver on, ignores chip enable control. 8 Read/Write Reserved 0 Reserved. Program 0. 9 Read/Write Reserved 0 Reserved. Program 0. REFERENCE DIVIDER (RDIV) REGISTER Table 19. Register 0x02, RDIV Register (Default 0x000001) Bits Type Name Default Description 13:0 Read/Write RDIV 1 Reference divider R value (see Equation 12). Using the divider requires the reference path buffer to be enabled (Register 0x08, Bit 3 = 1). 1 decimal ≤ RDIV ≤ 16,383 decimal. |
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