ADF5610 datasheet(11/51 Pages) AD

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Data Sheet

ADF5610

Rev. 0 | Page 11 of 51

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

GND 1

RVDD 2

GND 3

GND

NDIV_OUT

PDIV_OUT

VDD3

GND

RFOUT

GND

VCOVCC

VDD2

VPRST

GND

13 14

NOTES

1. EXPOSED PAD. THE EXPOSED PAD OR GROUND PADDLE ON THE BACKSIDE OF THE PACKAGE

MUST BE TIED TO DC GROUND FOR ELECTRICAL, MECHANICAL, AND THERMAL REASONS.

NOTE THAT RF GROUND AND DC GROUND ARE THE SAME IN THIS CASE.

15 16 17 18 19 20 21 22 23 24

VDDLS 4

GND 5

CP 6

GND 7

VPPCP 8

GND 9

AVDD 10

GND 11

GND 12

TOP VIEW

(Not to Scale)

ADF5610

Figure 2. Pin Configuration

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 3, 5, 7, 9, 11, 12, 14, 16,

18, 20, 22, 24 to 26,

30, 32, 36, 38, 40, 45,

GND

Ground.

RVDD

Reference Path Supply. 3.3 V ± 5%.

VDDLS

Power Supply for Charge Pump Digital Section. 3.3 V ± 5% typical, 3.6 V maximum. VDDLS must

be equal to VPPCP.

Charge Pump Output. Place first pole of low-pass loop filter close to this pin if loop filter path is

electrically long.

VPPCP

Power Supply for Charge Pump. 3.3 V ± 5% typical, 3.6 V maximum. VPPCP must be equal to

VDDLS.

AVDD

Analog Supply. 3.3 V ± 5%. AVDD must be equal to DVDD.

BIAS

External Bypass Decoupling for Precision Bias Circuits. Note that the 1.920 V ± 20 mV reference

voltage is generated internally and cannot drive an external load. The reference voltage must be

measured with a 10 GΩ meter, such as the Agilent 34410A. A normal 10 MΩ digital voltmeter

reads erroneously.

VCCPD

Phase Detector Supply. 3.3 V ± 5%.

VCCPS

Prescaler Supply. 3.3 V ± 5%.

SDO

Serial Data Output. Lock detect and various other functions are available via an internal mux.

VCCHF

Power Supply for PLL RF Section. 3.3 V ± 5%. Place a decoupling capacitor as close as possible to

this pin.

VDD1

Bias for VCO Digital Logic, VG Pin, SPI Buffer, and Input Buffer to PLL. Nominally 3.3 V ± 5%. Retain

bias to hold the VCO register contents when the VCO is powered down.

NDIV_OUT

Complementary Output of Differential Frequency Divider. N = 1, 2, 4, 8, 16, 32, 64, or 128. DC block

required. A broadband 100 nF capacitor is recommended.

PDIV_OUT

Primary Output of Differential Frequency Divider. N = 1, 2, 4, 8, 16, 32, 64, or 128. DC block

required. A broadband 100 nF capacitor is recommended.

VDD3

Differential Output Divider Supply. 3.3 V ± 5%.

RFOUT

RF Output (7300 MHz to 14,600 MHz). Internal dc block. DC block using a broadband 100 nF

capacitor.

VCOVCC

VCO Power Supply. 5.0 V ± 5%.

VDD2

Reference Voltage Supply. 3.3 V ± 5%.

VPRST

Temperature Dependent, Calibration Preset. Decouple with a 470 nF capacitor.

VCO Tuning Port. 0 V to 3.6 V, ± 5%. Place last pole of low-pass filtered charge pump output close

to this pin if loop filter path is electrically long.

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