ADF5610 datasheet(24/51 Pages) AD

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ADF5610

Data Sheet

Rev. 0 | Page 24 of 51

Table 35), written to the VCO subsystem via Register 0x05 =

000000001 0000 VCO_ID, where VCO_ID = 000b.

When autocalibration is enabled (Register 0x0A, Bit 11 = 0),

and a new frequency is written, autocalibration runs. The VCO

frequency error relative to the command frequency is measured

and the results are written to Register 0x11, Bits[19:0], where

terms of VCO count error (see Equation 4 through Equation 6).

Using generic values as an example, if the expected frequency at

the RFOUT pin is 7.0 GHz, the PFD frequency is 50 MHz, and

3500/(50/28) = 17,920 counts. Frequencies less than 8.0 GHz

route the fundamental frequency directly to the N counter.

Therefore, in this case, 3500 MHz is routed to the N counter.

For RFOUT frequencies greater than or equal to 8.0 GHz, the

internal prescaler of the PLL (Register 0x08, Bit 19) must be

enabled. If a difference of −5 counts is measured in Register 0x11,

that means 17,915 counts were actually measured. With a 7 GHz

VCO, 50 MHz reference, and n = 8, one count is 195.3125 kHz.

Therefore, the actual frequency of the VCO is low in frequency by

5 × 195.3 kHz for a fundamental frequency of 3499.0234375 MHz

or a push/push frequency of 6998.04687 MHz at RFOUT.

PLL SUBSYSTEM

Charge Pump (CP) and Phase Detector (PD)

The PD has two inputs, one from the reference path divider and

one from the RF path divider. When in lock, these two inputs

are at the same average frequency and are fixed at a constant

average phase offset with respect to each other. The frequency

of operation of the phase detector is fPD. Most formulas related

to step size, Δ-Σ modulation, and timers, are functions of the

operating frequency of the phase detector (fPD). The fPD is also

referred to as the comparison frequency of the phase detector.

The phase detector compares the phase of the RF path signal

with that of the reference path signal and controls the charge

pump output current as a linear function of the phase difference

between the two signals. The output current varies linearly over

a full ±2π radians (±360°) of input phase difference.

Charge Pump

A simplified diagram of the charge pump is shown in Figure 24.

The charge pump consists of four programmable current sources.

There are two sources controlling the charge pump gain (up gain,

and two sources controlling the charge pump offset, where the

magnitude of the offset is set by Register 0x09, Bits[20:14] and

the direction is selected by Register 0x09, Bit 21 = 1 for up offset

and Register 0x09, Bit 22 = 1 for down offset.

Charge pump gain is used at all times, whereas charge pump

offset is recommended for fractional mode only. Typically, the

charge pump up and charge pump down gain settings are set to

the same value (Register 0x09, Bits[13:7] = Register 0x09, Bits[6:0])

to minimize spurs.

Charge Pump Gain

Charge pump up and charge pump down gains are set by

The current gain of the pump in amps per radian is equal to the

gain setting of this register (Register 0x09) divided by 2π.

The typical CP gain setting is set from 2 mA to 2.5 mA.

However, lower values can also be used. Note that values less

than 1 mA may result in degraded phase noise performance.

For example, if both Register 0x09, Bits[13:7] and Register 0x09,

Bits[6:0] are set to 50 decimal, the output current of each pump

is 1 mA, and the phase frequency detector gain is kP = 1 mA/2π

radians, or 159 μA/rad. See the Charge Pump (CP) and Phase

Detector (PD) section for more information. Setting both the

charge pump up (Register 0x09, Bits[13:7] = 0) and charge pump

down (Register 0x09, Bits[6:0] = 0) tristates the charge pump.

Tristating can also be achieved using Register 0x0B. Refer to the

Phase Detector Functions section for more information.

Charge Pump Phase Offset

In integer mode, the phase detector operates with zero offset.

The divided reference signal and the divided VCO signal arrive

at the phase detector inputs at the same time. Integer mode does

not require any CP offset current. When operating in integer

mode, disable the CP offset in both directions (up and down)

by writing Register 0x09, Bits[22:21] = 00b, and set the CP offset

magnitude to zero by writing Register 0x09, Bits[20:14] = 0 decimal.

In fractional mode, CP linearity is of paramount importance.

Any nonlinearity degrades phase noise and spurious performance.

These nonlinearities are eliminated by operating the PD with an

average phase offset, either positive or negative (either the

reference or the VCO edge always leads or arrives at the PD).

A programmable CP offset current source adds dc current to

the loop filter and creates the desired phase offset. Positive

current causes the VCO to lead, whereas negative current

causes the reference to lead. Applications requiring an active

loop filter use the up offset, or positive offset. The ADF5610

uses a passive loop filter. Therefore, a down offset, or negative

offset, is recommended. Note that there can be conditions

where the offset that is not typically recommended may provide

improved spurious suppression, but these are often over very

narrow bandwidths.

The CP offset is controlled via Register 0x09. Increasing the

offset current causes the phase offset to scale from 0° to 360°.

The specific level of the charge pump offset current (Register 0x09,

Bits[20:14]) is calculated using Equation 9 and shown in Figure 23.

Required CP Offset = min ((4.3 × 10−9 × fPD × ICP), 0.25 × ICP) (9)

where:

fPD is the comparison frequency of the phase detector (Hz).

ICP is the full-scale current setting (A) of the switching charge

pump (set in Register 0x09, Bits[6:0] and Register 0x09,

Bits[13:7]).

ADF5610 Datasheet(PDF) 24 Page - Analog Devices

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