ADF5610 datasheet(29/51 Pages) AD

29 / 51 page

Data Sheet

ADF5610

Rev. 0 | Page 29 of 51

Fractional Mode

Set the following registers to place the ADF5610 in fractional

mode:

•

Enable the fractional modulator, Register 0x06, Bit 11 = 1.

•

Connect the Δ-Σ modulator in circuit, Register 0x06, Bit 7 = 0.

Fractional Frequency Tuning

This sections provides a generic example with the goal of

explaining how to program the output frequency. Actual

variables are dependent on the reference in use.

The ADF5610 in fractional mode achieves frequencies at

fractional multiples of the reference. The frequency of the

ADF5610 is given by the following equation:

fRF = 2 × fVCO

where:

()

XTAL

VCO

INT

FRAC

INT

FRAC

(12)

and

fDIV = fRF/k

(13)

where:

fRF is the doubled frequency (RFOUT).

fVCO is the fundamental frequency (input to PLL) after any

necessary correction. The fVCO value must always be less than or

equal to 4000 MHz. When fVCO is greater than or equal to 4000

MHz, the internal divide by 2 prescaler (Register 0x08, Bit 19)

must be enabled.

fXTAL is the frequency at the reference oscillator input.

R is the reference path division ratio (set in Register 0x02).

NINT is the integer division ratio (set in Register 0x03), an

integer number between 20 and 524,284.

NFRAC is the fractional part, from 0.0 to 0.99999…, NFRAC =

fDIV is the output frequency after any potential dividers.

k is 1 for fundamental, or k = 2 to 128 depending on the

selected output divider value (Register 0x05, Bits[9:7] indirectly

address VCO Register 0x02, Bits[2:0]).

For example, fDIV = 1752.5 MHz, k = 4, fVCO = 3505 MHz, fRF =

7010 MHz, fXTAL = 50 MHz, R = 1, fPD = 50 MHz, NINT = 70, and

NFRAC = 0.1. The fPD value is the PD operating frequency, fXTAL/R.

1,677,722.

If fVCO

≤ 4000 MHz, then Register 0x08, Bit 19 = 0 (divide by 1).

If fVCO > 4000 MHz, then Register 0x08, Bit 19 = 1.

fVCO (50 × 106/1) (70 + 1677722/224) = 3505 MHz +

1.192 Hz error

(14)

fRF = 2 × fVCO = 7010 MHz + 2.384 Hz error

(15)

fDIV = fRF/k = (7010 MHz + 2.384 Hz error)/4 =

1752.5 MHz + 0.596 Hz error

(16)

In this example, the differential divider output frequency of

1752.5 MHz is achieved by programming the 19-bit binary value

of 70 decimal = 0x46 into the INTG_REG bit in Register 0x03,

and the 24-bit binary value of 1677722 decimal = 0x19999A

into the FRAC bit in Register 0x04. Eliminate the 0.596 Hz

quantization error using the exact frequency mode, if required.

In this example, the RFOUT value is divided by 4. Specific control

of the output divider is required. See the VCO Subsystem

Exact Frequency Tuning

Due to quantization effects, the absolute frequency precision of

a fractional PLL is normally limited by the number of bits in the

fractional modulator. For example, the frequency resolution of a

24-bit fractional modulator is set by the PD comparison rate

divided by 224. The 224 value in the denominator is sometimes

referred to as the modulus. Analog Devices PLLs use a fixed

modulus, which is a binary number. In some types of fractional

PLLs, the modulus is variable, allowing exact frequency steps to

be achieved with decimal step sizes. Unfortunately, small steps

using small modulus values result in large spurious outputs at

multiples of the modulus period (channel step size). For this

reason, Analog Devices PLLs use a large fixed modulus. Normally,

the step size is set by the size of the fixed modulus. In the case

of a 50 MHz PD rate, a modulus of 224 results in a 2.98 Hz step

resolution, or 0.0596 ppm. In some applications, it is necessary

to have exact frequency steps, and even an error of 3 Hz cannot

be tolerated.

Fractional PLLs are able to generate exact frequencies (with zero

frequency error) if N can be exactly represented in binary (for

example, N = 50.0, 50.5, 50.25, 50.75). Some common frequencies

cannot be exactly represented. For example, NFRAC = 0.1 = 1/10

must be approximated as round((0.1 × 224)/224) ≈ 0.100000024.

At fPD = 50 MHz, the NFRAC value translates to a 1.2 Hz error.

The exact frequency mode of the ADF5610 addresses this issue

and can eliminate quantization error by programming the

channel step size to fPD/10 in Register 0x0C to 10 (in this example).

More generally, this feature can be used whenever the desired

frequency (fVCO) can be exactly represented on a step plan where

there is an integer number of steps (<214) across Integer N

boundaries. Mathematically, this situation is satisfied if

fVCOk mod(fGCD) = 0

(17)

where:

fVCOk is the channel step frequency, 0 < k < 224 − 1, as shown in

Figure 26.

GCD is the greatest common divisor.













≥

and

)

(

GCD

VCO

GCD

where fPD is the frequency of the phase detector.

Some fractional PLLs are able to achieve these exact frequencies

by shortening the length of the phase accumulator (the

denominator or the modulus of the Δ-Σ modulator) so that the

Δ-Σ modulator phase accumulator repeats at an exact period

ADF5610 Datasheet(PDF) 29 Page - Analog Devices

ADF5610 Datasheet(HTML) 29 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

Datasheet Download

Link URL