DM368ZCEZ datasheet(26/208 Pages) TI1

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TMS320DM368

SPRS668C

– APRIL 2010 – REVISED JUNE 2011

www.ti.com

Table 2-5. Pin Descriptions (continued)

Name

BGA

Type

Group

Power

IPU

Reset

Description(4)

(1)

Supply(2)

IPD(3)

State

GIO88 /

D16

I/O

GIO /

VDDS33

Input

GIO: GIO[88]

COUT3(B6) (12)/

VENC /

PWM2 / RTO2

PWM2 /

RTO2

Digital Video Out: VENC settings determine

function(13).

For more details, see the DM36x DMSoC Video

Processor Back End User's Guide (SPRUFG9).

PWM2: PWM2 Output

RTO2: RTO2 Output

GIO87 /

D19

I/O

GIO /

VDDS33

Input

GIO: GIO[87]

COUT2(B5)(12) /

VENC

PWM2 / RTO3

/PWM2

/ RTO3

Digital Video Out: VENC settings determine

function(13).

For more details, see the DM36x DMSoC Video

Processor Back End User's Guide (SPRUFG9).

PWM2: PWM2 Output

RTO3: RTO3 Output

GIO86 /

D18

I/O

GIO /

VDDS33

Input

GIO: GIO[86]

COUT1(B4)(12) /

VENC /

PWM3 / STTRIG

PWM3

Digital Video Out: VENC settings determine

function(13).

For more details, see the DM36x DMSoC Video

Processor Back End User's Guide (SPRUFG9).

PWM3: PWM3 Output

STTRIG: Camera FLASH control trigger signal

GIO85 /

D17

I/O

GIO /

VDDS33

Input

GIO: GIO[85]

COUT0(B3) (14)/

VENC /

PWM3

Digital Video Out: VENC settings determine

function(15).

For more details, see the DM36x DMSoC Video

Processor Back End User's Guide (SPRUFG9).

PWM3: PWM3 Output

GIO81(OSCCFG) /

C18

I/O

GIO /

VDDS33

Input

GIO: GIO[81]

LCD_FIELD / R2 /

VENC /

Note: This pin will be used as oscillator configuration

PWM3

(OSCCFG). The GIO81(OSCCFG) state is latched

during reset, and it specifies the oscillation frequency

range mode of the pin. See Section 3.7.6 for more

details.

Video Encoder: Field identifier for interlaced display

formats(15).

For more details, see the DM36x DMSoC Video

Processor Back End User's Guide (SPRUFG9).

Digital Video Out: R2(15)

PWM3: PWM3 Output

(14) The Y output (YOUT[7:0]) and C output (COUT[7:0]) buses can be swapped by programming the field bit YCOUTSWP in the VPFE

CCD Configuration (CCDCFG) register (0x01C7 0136h). If the YCOUTSWP bit is 0 (default), YOUT[7:0] = Y signal / COUT[7:0] = C

signal . If the YCOUTSWP bit is 1, YOUT[7:0] = C signal / COUT[7:0] = Y signal. For more information, see the TMS320DM36x Video

Processing Front End (VPFE) Reference Guide (literature number SPRUFG8).

(15) To reduce EMI and reflections, depending on the trace length, approximately 22

Ω to 50 Ω damping resistors are recommend on the

following outputs placed near the device: YOUT(0-7),COUT(0-7), HSYNC,VSYNC,LCD_OE,FIELD, and,VCLK. The trace lengths should

be minimized.

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