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DM368ZCEZ Datasheet(PDF) 56 Page - Texas Instruments |
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DM368ZCEZ Datasheet(HTML) 56 Page - Texas Instruments |
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56 / 208 page  TMS320DM368 SPRS668C – APRIL 2010 – REVISED JUNE 2011 www.ti.com • PLL bypass • PLL power down The various clock outputs given by the PLL controller are as follows: • Domain clocks: SYSCLKn • Bypass domain clock: SYSCLKBP • Auxiliary clock from reference clock: AUXCLK Various dividers that can be used are as follows: • Pre-PLL divider: PREDIV • Post-PLL divider: POSTDIV • SYSCLK divider: PLLDIV1, …, PLLDIVn • SYSCLKBP divider: BPDIV The Multiplier values supported are handled by: • PLL multiplier control: PLLM Notes: • PLLCxSYSCLKy is used to denote post divide clock output SYSCLKy from PLL controller x • 'x', which denotes PLL Controller number, can assume values 1 and 2 • 'y', which denotes post divide clock outputs, can assume values 1 to 9 in case of PLLC1 and 1 to 5 in case of PLLC2 The PLL Controllers for PLL1 and PLL2 are described in detail in the TMS320DM36x ARM Subsystem Reference Guide (literature number SPRUFG5). 56 Device Configurations Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM368 |
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