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DM368ZCEZ Datasheet(PDF) 80 Page - Texas Instruments |
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DM368ZCEZ Datasheet(HTML) 80 Page - Texas Instruments |
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80 / 208 page  1 2 3 RESET BootConfigurationPins (BTSEL[2:0],AECFG[2:0]) TMS320DM368 SPRS668C – APRIL 2010 – REVISED JUNE 2011 www.ti.com 6.5 Reset 6.5.1 Reset Electrical Data/Timing Table 6-2. Timing Requirements for Reset (1) (2) (3) (see Figure 6-4) DEVICE NO. UNIT MIN MAX 1 tw(RESET) Active low width of the RESET pulse 12C ns 2 tsu(BOOT) Setup time, boot configuration pins valid before RESET rising edge 2E ns 3 th(BOOT) Hold time, boot configuration pins valid after RESET rising edge 0 ns (1) BTSEL[2:0] and AECFG[2:0] are the boot configuration pins during device reset. (2) C = MXI1/CLKIN cycle time in ns. For example, when MXI1/CLKIN frequency is 24 MHz use C = 41.6 ns. (3) E = 1/PLLC1SYSCLK4 cycle time in ns. Figure 6-4. Reset Timing 80 Peripheral Information and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM368 |
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