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TAS2564 Datasheet(PDF) 3 Page - Texas Instruments |
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TAS2564 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 118 page ![]() A3 FSYNC C2 VBAT C3 VS1_N D3 BGND C4 GREG D4 GND F3 VBST C5 VS1_P/ VS2_N D5 PGND E6 OUT_N A6 DREG C6 VS2_P D6 PGND B6 VDD F5 PVDD F6 PVDD D2 BGND B2 SDIN E2 SW F2 VBST E4 GND E5 OUT_P E3 SW A5 SDA B3 AD1 F4 PVDD B4 AD0 A4 SCL B5 IRQZ C1 VBAT D1 BGND E1 SW A2 SBCLK F1 VBST B1 SDOUT A1 SDZ 3 TAS2564 www.ti.com SLASEI6A – OCTOBER 2019 – REVISED DECEMBER 2019 Product Folder Links: TAS2564 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated 5 Pin Configuration and Functions YFP Package 36-Pin DSBGA Top View Pin Functions PIN I/O DESCRIPTION NAME NUMBER AD0 B4 I I2C address pin LSB. AD1 B3 I I2C address pin LSB+1. BGND D1 P Boost ground. Connect to PCB GND plane. D2 D3 DREG A6 P Digital core voltage regulator output. Bypass to GND with a cap. Do not connect to external load. FSYNC A3 IO I2S word clock or TDM frame sync. GREG C4 P High-side gate CP regulator output. Do not connect to external load. GND D4 P Digital ground. Connect to PCB GDN plane. E4 IRQZ B5 O Open drain, active low interrupt pin. Pull up to VDDD with resistor if optional internal pull up is not used. OUT_N E6 O Class-D negative output. OUT_P E5 O Class-D positive output. |
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