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TAS2564 Datasheet(PDF) 12 Page - Texas Instruments |
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TAS2564 Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 118 page  FSYNC SBCLK tH(SBCLK) tL(SBCLK) tr(SBCLK) tf(SBCLK) tSU(FSYNC) tHLD(FSYNC) tSU(SDIN) tHLD(SDIN) td(DO-FSYNC) td(DO-SBCLK) SDIN SDOUT tBUF STO STA th(STA) tLOW tr th(DAT) tf tHIGH tsu(DAT) SDA SCL tsu(STA) STA th(STA) STO tsu(STO) 12 TAS2564 SLASEI6A – OCTOBER 2019 – REVISED DECEMBER 2019 www.ti.com Product Folder Links: TAS2564 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated TDM Port Timing Requirements (continued) TA = 25 °C, VDD = 1.8 V, 20 pF load on all outputs (unless otherwise noted) MIN NOM MAX UNIT tHLD(FSYNC) FSYNC hold time 8 ns tSU(FSYNC) SDIN setup time 8 ns tHLD(SDIN) SDIN hold time 8 ns td(DO-SBCLK) SBCLK to SDOUT delay 50% of FSYNC to 50% of SDOUT 21 ns tr(SBCLK) SBCLK rise time 10% - 90 % Rise Time 8 ns tf(SBCLK) SBCLK fall time 90% - 10 % Fall Time 8 ns Figure 1. I2C Timing Diagram Figure 2. TDM Timing Diagram |
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