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TAS2564 Datasheet(PDF) 11 Page - Texas Instruments |
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TAS2564 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 118 page  11 TAS2564 www.ti.com SLASEI6A – OCTOBER 2019 – REVISED DECEMBER 2019 Product Folder Links: TAS2564 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated 6.6 I 2C Timing Requirements TA = 25 °C, VDD = 1.8 V (unless otherwise noted) MIN NOM MAX UNIT Standard-Mode fSCL SCL clock frequency 0 100 kHz tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 4 μs tLOW LOW period of the SCL clock 4.7 μs tHIGH HIGH period of the SCL clock 4 μs tSU;STA Setup time for a repeated START condition 4.7 μs tHD;DAT Data hold time: For I2C bus devices 0 3.45 μs tSU;DAT Data set-up time 250 ns tr SDA and SCL rise time 1000 ns tf SDA and SCL fall time 300 ns tSU;STO Set-up time for STOP condition 4 μs tBUF Bus free time between a STOP and START condition 4.7 μs Cb Capacitive load for each bus line 400 pF Fast-Mode fSCL SCL clock frequency 0 400 kHz tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 0.6 μs tLOW LOW period of the SCL clock 1.3 μs tHIGH HIGH period of the SCL clock 0.6 μs tSU;STA Setup time for a repeated START condition 40.6 μs tHD;DAT Data hold time: For I2C bus devices 0 0.9 μs tSU;DAT Data set-up time 100 ns tr SDA and SCL rise time 20 + 0.1 × Cb 300 ns tf SDA and SCL fall time 20 + 0.1 × Cb 300 ns tSU;STO Set-up time for STOP condition 0.6 μs tBUF Bus free time between a STOP and START condition 1.3 μs Cb Capacitive load for each bus line 400 pF Fast-Mode Plus fSCL SCL clock frequency 0 1000 kHz tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 0.26 μs tLOW LOW period of the SCL clock 0.5 μs tHIGH HIGH period of the SCL clock 0.26 μs tSU;STA Setup time for a repeated START condition 0.26 μs tHD;DAT Data hold time: For I2C bus devices 0 μs tSU;DAT Data set-up time 50 ns tr SDA and SCL Rise Time 120 ns tf SDA and SCL Fall Time 120 ns tSU;STO Set-up time for STOP condition μs tBUF Bus free time between a STOP and START condition 0.5 μs Cb Capacitive load for each bus line 400 pF 6.7 TDM Port Timing Requirements TA = 25 °C, VDD = 1.8 V, 20 pF load on all outputs (unless otherwise noted) MIN NOM MAX UNIT tH(SBCLK) SBCLK high period 20 ns tL(SBCLK) SBCLK low period 20 ns tSU(FSYNC) FSYNC setup time 8 ns |
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