SC16C752 datasheet(21/47 Pages) PHILIPS

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Philips Semiconductors

SC16C752

Dual UART with 64-byte FIFO

Product data

Rev. 04 — 20 June 2003

21 of 47

9397 750 11635

7.3 FIFO control register (FCR)

This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs,

setting transmitter and receiver trigger levels, and selecting the type of DMA

signalling. Table 11 shows FIFO control register bit settings.

Table 11:

FIFO Control Register bits description

Bit

Symbol

Description

7-6

FCR[7]

(MSB),

FCR[6]

(LSB)

RCVR trigger. Sets the trigger level for the RX FIFO.

00 - 8 characters

01 - 16 characters

10 - 56 characters

11 - 60 characters

5-4

FCR[5]

(MSB),

FCR[4]

(LSB)

TX trigger. Sets the trigger level for the TX FIFO.

00 - 8 spaces

01 - 16 spaces

10 - 32 spaces

11 - 56 spaces

FCR[5-4] can only be modiﬁed and enabled when EFR[4] is set. This is

because the transmit trigger level is regarded as an enhanced function.

FCR[3]

DMA mode select.

Logic 0 = Set DMA mode ‘0’

Logic 1 = Set DMA mode ‘1’

FCR[2]

Reset TX FIFO.

Logic 0 = No FIFO transmit reset (normal default condition).

Logic 1 = Clears the contents of the transmit FIFO and resets the

FIFO counter logic (the transmit shift register is not cleared or

altered). This bit will return to a logic 0 after clearing the FIFO.

FCR[1]

Reset RX FIFO.

Logic 0 = No FIFO receive reset (normal default condition).

Logic 1 = Clears the contents of the receive FIFO and resets the FIFO

counter logic (the receive shift register is not cleared or altered). This

bit will return to a logic 0 after clearing the FIFO.

FCR[0]

FIFO enable.

Logic 0 = Disable the transmit and receive FIFO (normal default

condition).

Logic 1 = Enable the transmit and receive FIFO.

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