M263 datasheet(327/398 Pages) NUVOTON

327 / 398 page

M261/M262/M263

Mar 25, 2020

Page 327 of 398

Rev 1.02

6.27

Secure Digital Host Controller (SDH)

6.27.1

Overview

The Secure Digital Host Controller (SD Host) has DMAC unit and SD unit. The DMAC unit provides a

DMA (Direct Memory Access) function for SD to exchange data between system memory and shared

buffer (128 bytes), and the SD unit controls the interface of SD/SDHC. The SDHOST controller can

support SD/SDHC and cooperated with DMAC to provide a fast data transfer between system memory

and cards.

6.27.2

Features



AMBA AHB master/slave interface compatible, for data transfer and register read/write.



Supports single DMA channel.



Supports hardware Scatter-Gather function.



Using single 128 Bytes shared buffer for data exchange between system memory and

cards.



Synchronous design for DMA with single clock domain, AHB bus clock (HCLK).



Interface with DMAC for register read/write and data transfer.



Supports SD/SDHC card.



Completely asynchronous design for Secure Digital with two clock domains, HCLK and

Engine clock, note that frequency of HCLK should be higher than the frequency of

peripheral clock.

M263 Datasheet(PDF) 327 Page - Nuvoton Technology Corporation